Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5277	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1873	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2055	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2022	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1918	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2110	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1971	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1962	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1974	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2068	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1875	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1967	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2017	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2023	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1941	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1945	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2089	0	0
adc_en_ctl_rd_A	2147483647	1565	0	0
adc_fsm_rst_rd_A	2147483647	1347	0	0
adc_intr_ctl_rd_A	2147483647	1390	0	0
adc_lp_sample_ctl_rd_A	2147483647	1457	0	0
adc_pd_ctl_rd_A	2147483647	1809	0	0
adc_sample_ctl_rd_A	2147483647	1362	0	0
adc_wakeup_ctl_rd_A	2147483647	1361	0	0
intr_enable_rd_A	2147483647	2018	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5277	0	0
T2	9920	2	0	0
T3	4213	0	0	0
T4	186833	0	0	0
T7	52701	0	0	0
T8	31082	0	0	0
T9	382137	0	0	0
T10	582289	0	0	0
T11	67694	0	0	0
T12	107419	0	0	0
T27	17146	0	0	0
T35	0	531	0	0
T52	0	762	0	0
T53	0	2	0	0
T54	0	206	0	0
T55	0	512	0	0
T56	0	272	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1873	0	0
T7	52701	0	0	0
T8	31082	5	0	0
T9	382137	0	0	0
T10	582289	97	0	0
T11	67694	14	0	0
T12	107419	0	0	0
T23	27329	0	0	0
T24	38150	0	0	0
T26	0	191	0	0
T27	17146	0	0	0
T34	7583	3	0	0
T35	0	12	0	0
T53	0	206	0	0
T67	0	66	0	0
T84	0	46	0	0
T173	0	6	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T7	52701	0	0	0
T8	31082	8	0	0
T9	382137	0	0	0
T10	582289	95	0	0
T11	67694	6	0	0
T12	107419	0	0	0
T23	27329	0	0	0
T24	38150	0	0	0
T26	0	252	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	16	0	0
T53	0	223	0	0
T67	0	78	0	0
T68	0	14	0	0
T84	0	25	0	0
T173	0	7	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2022	0	0
T7	52701	0	0	0
T8	31082	3	0	0
T9	382137	0	0	0
T10	582289	129	0	0
T11	67694	12	0	0
T12	107419	0	0	0
T23	27329	3	0	0
T24	38150	0	0	0
T26	0	176	0	0
T27	17146	0	0	0
T34	7583	15	0	0
T35	0	11	0	0
T53	0	229	0	0
T84	0	33	0	0
T173	0	14	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T7	52701	0	0	0
T8	31082	9	0	0
T9	382137	0	0	0
T10	582289	67	0	0
T11	67694	0	0	0
T12	107419	0	0	0
T23	27329	4	0	0
T24	38150	0	0	0
T26	0	194	0	0
T27	17146	0	0	0
T34	7583	5	0	0
T35	0	19	0	0
T53	0	185	0	0
T67	0	61	0	0
T84	0	45	0	0
T173	0	12	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2110	0	0
T10	582289	89	0	0
T11	67694	9	0	0
T12	107419	0	0	0
T23	27329	1	0	0
T24	38150	0	0	0
T25	50665	0	0	0
T26	0	236	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	19	0	0
T53	0	175	0	0
T66	60972	0	0	0
T67	0	74	0	0
T68	0	13	0	0
T84	0	74	0	0
T173	0	6	0	0
T174	9525	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T7	52701	0	0	0
T8	31082	5	0	0
T9	382137	0	0	0
T10	582289	89	0	0
T11	67694	15	0	0
T12	107419	0	0	0
T23	27329	0	0	0
T24	38150	0	0	0
T26	0	191	0	0
T27	17146	0	0	0
T34	7583	7	0	0
T35	0	1	0	0
T53	0	225	0	0
T67	0	103	0	0
T84	0	37	0	0
T173	0	15	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T7	52701	0	0	0
T8	31082	17	0	0
T9	382137	0	0	0
T10	582289	133	0	0
T11	67694	0	0	0
T12	107419	0	0	0
T23	27329	15	0	0
T24	38150	0	0	0
T26	0	172	0	0
T27	17146	0	0	0
T34	7583	5	0	0
T35	0	4	0	0
T53	0	207	0	0
T67	0	85	0	0
T84	0	19	0	0
T173	0	7	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T7	52701	0	0	0
T8	31082	5	0	0
T9	382137	0	0	0
T10	582289	93	0	0
T11	67694	18	0	0
T12	107419	0	0	0
T23	27329	7	0	0
T24	38150	0	0	0
T26	0	134	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	14	0	0
T53	0	249	0	0
T67	0	99	0	0
T84	0	9	0	0
T173	0	5	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T7	52701	0	0	0
T8	31082	20	0	0
T9	382137	0	0	0
T10	582289	123	0	0
T11	67694	24	0	0
T12	107419	0	0	0
T23	27329	41	0	0
T24	38150	0	0	0
T26	0	205	0	0
T27	17146	0	0	0
T34	7583	2	0	0
T35	0	19	0	0
T53	0	185	0	0
T84	0	19	0	0
T173	0	10	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T7	52701	0	0	0
T8	31082	2	0	0
T9	382137	0	0	0
T10	582289	107	0	0
T11	67694	2	0	0
T12	107419	0	0	0
T23	27329	5	0	0
T24	38150	0	0	0
T26	0	206	0	0
T27	17146	0	0	0
T34	7583	8	0	0
T35	0	5	0	0
T53	0	202	0	0
T84	0	29	0	0
T173	0	9	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T7	52701	0	0	0
T8	31082	21	0	0
T9	382137	0	0	0
T10	582289	121	0	0
T11	67694	2	0	0
T12	107419	0	0	0
T23	27329	0	0	0
T24	38150	0	0	0
T26	0	187	0	0
T27	17146	0	0	0
T34	7583	3	0	0
T53	0	201	0	0
T67	0	84	0	0
T68	0	2	0	0
T84	0	26	0	0
T173	0	8	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2017	0	0
T7	52701	0	0	0
T8	31082	11	0	0
T9	382137	0	0	0
T10	582289	123	0	0
T11	67694	0	0	0
T12	107419	0	0	0
T23	27329	3	0	0
T24	38150	0	0	0
T26	0	209	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	14	0	0
T53	0	148	0	0
T67	0	86	0	0
T68	0	15	0	0
T84	0	34	0	0
T173	0	7	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2023	0	0
T7	52701	0	0	0
T8	31082	2	0	0
T9	382137	0	0	0
T10	582289	119	0	0
T11	67694	3	0	0
T12	107419	0	0	0
T23	27329	10	0	0
T24	38150	0	0	0
T26	0	190	0	0
T27	17146	0	0	0
T34	7583	15	0	0
T35	0	8	0	0
T53	0	206	0	0
T84	0	28	0	0
T173	0	16	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1941	0	0
T7	52701	0	0	0
T8	31082	16	0	0
T9	382137	0	0	0
T10	582289	76	0	0
T11	67694	19	0	0
T12	107419	0	0	0
T23	27329	33	0	0
T24	38150	0	0	0
T26	0	171	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	8	0	0
T53	0	253	0	0
T67	0	80	0	0
T84	0	6	0	0
T173	0	7	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1945	0	0
T7	52701	0	0	0
T8	31082	3	0	0
T9	382137	0	0	0
T10	582289	91	0	0
T11	67694	29	0	0
T12	107419	0	0	0
T23	27329	15	0	0
T24	38150	0	0	0
T26	0	221	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	3	0	0
T53	0	145	0	0
T67	0	80	0	0
T84	0	22	0	0
T173	0	21	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2089	0	0
T7	52701	0	0	0
T8	31082	6	0	0
T9	382137	0	0	0
T10	582289	71	0	0
T11	67694	0	0	0
T12	107419	0	0	0
T23	27329	12	0	0
T24	38150	0	0	0
T26	0	194	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	7	0	0
T53	0	228	0	0
T67	0	62	0	0
T68	0	22	0	0
T84	0	74	0	0
T173	0	10	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T7	52701	0	0	0
T8	31082	6	0	0
T9	382137	0	0	0
T10	582289	59	0	0
T11	67694	10	0	0
T12	107419	0	0	0
T23	27329	18	0	0
T24	38150	0	0	0
T26	0	121	0	0
T27	17146	0	0	0
T34	7583	4	0	0
T35	0	10	0	0
T53	0	92	0	0
T84	0	74	0	0
T173	0	9	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1347	0	0
T7	52701	0	0	0
T8	31082	7	0	0
T9	382137	0	0	0
T10	582289	26	0	0
T11	67694	14	0	0
T12	107419	0	0	0
T23	27329	25	0	0
T24	38150	0	0	0
T26	0	85	0	0
T27	17146	0	0	0
T34	7583	13	0	0
T35	0	3	0	0
T53	0	66	0	0
T84	0	28	0	0
T173	0	15	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1390	0	0
T7	52701	0	0	0
T8	31082	3	0	0
T9	382137	0	0	0
T10	582289	32	0	0
T11	67694	15	0	0
T12	107419	0	0	0
T23	27329	19	0	0
T24	38150	0	0	0
T26	0	67	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	13	0	0
T53	0	68	0	0
T67	0	116	0	0
T84	0	40	0	0
T173	0	1	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1457	0	0
T7	52701	0	0	0
T8	31082	4	0	0
T9	382137	0	0	0
T10	582289	48	0	0
T11	67694	15	0	0
T12	107419	0	0	0
T23	27329	8	0	0
T24	38150	0	0	0
T26	0	68	0	0
T27	17146	0	0	0
T34	7583	4	0	0
T35	0	3	0	0
T53	0	81	0	0
T84	0	53	0	0
T173	0	10	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1809	0	0
T7	52701	0	0	0
T8	31082	12	0	0
T9	382137	0	0	0
T10	582289	84	0	0
T11	67694	19	0	0
T12	107419	0	0	0
T23	27329	18	0	0
T24	38150	0	0	0
T26	0	176	0	0
T27	17146	0	0	0
T34	7583	1	0	0
T35	0	12	0	0
T53	0	152	0	0
T84	0	35	0	0
T173	0	12	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1362	0	0
T7	52701	0	0	0
T8	31082	2	0	0
T9	382137	0	0	0
T10	582289	33	0	0
T11	67694	12	0	0
T12	107419	0	0	0
T23	27329	0	0	0
T24	38150	0	0	0
T26	0	75	0	0
T27	17146	0	0	0
T34	7583	0	0	0
T35	0	7	0	0
T53	0	85	0	0
T67	0	84	0	0
T68	0	66	0	0
T84	0	52	0	0
T173	0	10	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1361	0	0
T7	52701	0	0	0
T8	31082	2	0	0
T9	382137	0	0	0
T10	582289	53	0	0
T11	67694	7	0	0
T12	107419	0	0	0
T23	27329	11	0	0
T24	38150	0	0	0
T26	0	89	0	0
T27	17146	0	0	0
T34	7583	6	0	0
T35	0	19	0	0
T53	0	65	0	0
T84	0	48	0	0
T173	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2018	0	0
T7	52701	0	0	0
T8	31082	8	0	0
T9	382137	0	0	0
T10	582289	29	0	0
T11	67694	14	0	0
T12	107419	0	0	0
T23	27329	15	0	0
T24	38150	0	0	0
T26	0	79	0	0
T27	17146	28	0	0
T34	7583	8	0	0
T35	0	6	0	0
T53	0	82	0	0
T62	0	8	0	0