Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1070928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1031416

1

T5

63

T6

77

T7

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1839669	1			T5	18		T6	59		T7	19
values[0x0]	130733	1			T5	32		T6	37		T7	13
values[0x1]	131942	1			T5	30		T6	28		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	862609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1239735

1

T5

72

T6

89

T7

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6146	1			T28	2		T10	4		T14	14
valid_sources[0x01]	10232	1			T28	3		T30	1		T11	1
valid_sources[0x02]	10622	1			T26	2		T2	4		T10	7
valid_sources[0x03]	6289	1			T26	1		T4	1		T30	1
valid_sources[0x04]	9423	1			T5	3		T26	2		T10	4
valid_sources[0x05]	6445	1			T26	1		T10	12		T14	13
valid_sources[0x06]	7238	1			T26	3		T28	1		T30	1
valid_sources[0x07]	7083	1			T26	1		T4	1		T9	1
valid_sources[0x08]	7240	1			T26	2		T4	2		T28	1
valid_sources[0x09]	6432	1			T2	1		T4	1		T28	1
valid_sources[0x0a]	10806	1			T28	1		T10	5		T67	1
valid_sources[0x0b]	6264	1			T2	1		T12	2		T13	1
valid_sources[0x0c]	6441	1			T6	6		T26	1		T2	2
valid_sources[0x0d]	10363	1			T26	6		T3	1		T10	53
valid_sources[0x0e]	6249	1			T26	6		T3	1		T28	1
valid_sources[0x0f]	13592	1			T6	19		T2	2		T3	1
valid_sources[0x10]	6021	1			T26	4		T28	4		T10	4
valid_sources[0x11]	8138	1			T26	1		T4	1		T28	4
valid_sources[0x12]	10481	1			T4	1		T28	5		T29	4
valid_sources[0x13]	6705	1			T6	34		T2	2		T4	2
valid_sources[0x14]	6336	1			T26	3		T4	1		T28	1
valid_sources[0x15]	6464	1			T26	1		T4	1		T28	9
valid_sources[0x16]	6114	1			T26	1		T2	2		T29	2
valid_sources[0x17]	15824	1			T5	2		T26	3		T3	2
valid_sources[0x18]	14695	1			T26	2		T4	1		T28	2
valid_sources[0x19]	7106	1			T2	2		T3	1		T9	2
valid_sources[0x1a]	6454	1			T26	2		T8	2		T12	28
valid_sources[0x1b]	21066	1			T26	1		T3	4		T28	1
valid_sources[0x1c]	5946	1			T26	1		T10	1		T11	8
valid_sources[0x1d]	5938	1			T26	6		T10	4		T9	5
valid_sources[0x1e]	5967	1			T28	2		T30	3		T9	7
valid_sources[0x1f]	8832	1			T5	4		T26	4		T2	1
valid_sources[0x20]	7803	1			T5	3		T26	1		T27	31
valid_sources[0x21]	6371	1			T26	1		T3	1		T28	1
valid_sources[0x22]	7065	1			T26	1		T4	1		T28	2
valid_sources[0x23]	6145	1			T26	2		T4	1		T28	3
valid_sources[0x24]	9211	1			T2	2		T29	1		T9	7
valid_sources[0x25]	10392	1			T7	2		T28	3		T29	5
valid_sources[0x26]	7052	1			T26	3		T2	3		T30	1
valid_sources[0x27]	14615	1			T26	1		T4	1		T11	2
valid_sources[0x28]	6080	1			T2	3		T4	2		T28	2
valid_sources[0x29]	9341	1			T26	2		T4	2		T10	46
valid_sources[0x2a]	6404	1			T26	3		T2	1		T3	3
valid_sources[0x2b]	6360	1			T26	1		T2	2		T4	1
valid_sources[0x2c]	7289	1			T7	18		T26	1		T11	1
valid_sources[0x2d]	6276	1			T26	1		T28	2		T8	4
valid_sources[0x2e]	7090	1			T4	1		T29	2		T12	6
valid_sources[0x2f]	6301	1			T5	1		T26	2		T28	7
valid_sources[0x30]	7174	1			T2	3		T3	7		T4	1
valid_sources[0x31]	7082	1			T7	3		T26	3		T2	1
valid_sources[0x32]	8684	1			T5	7		T8	2		T10	1
valid_sources[0x33]	7058	1			T26	1		T3	1		T30	2
valid_sources[0x34]	6367	1			T26	2		T3	3		T28	1
valid_sources[0x35]	6424	1			T5	2		T28	4		T30	1
valid_sources[0x36]	6634	1			T26	2		T12	4		T14	11
valid_sources[0x37]	13603	1			T6	2		T26	1		T14	19
valid_sources[0x38]	26200	1			T26	1		T4	1		T28	2
valid_sources[0x39]	20046	1			T26	1		T2	1		T4	1
valid_sources[0x3a]	10233	1			T5	1		T3	1		T4	1
valid_sources[0x3b]	10631	1			T28	2		T30	1		T10	5
valid_sources[0x3c]	6399	1			T26	2		T2	4		T9	3
valid_sources[0x3d]	7445	1			T26	1		T2	1		T28	3
valid_sources[0x3e]	6309	1			T5	1		T3	3		T9	6
valid_sources[0x3f]	10425	1			T26	1		T3	6		T4	2
valid_sources[0x40]	6272	1			T26	3		T30	1		T10	4
valid_sources[0x41]	6075	1			T26	1		T2	1		T4	2
valid_sources[0x42]	6094	1			T26	1		T2	2		T30	1
valid_sources[0x43]	6472	1			T5	1		T26	1		T2	3
valid_sources[0x44]	6253	1			T30	1		T9	6		T14	20
valid_sources[0x45]	6241	1			T2	2		T3	1		T11	2
valid_sources[0x46]	5944	1			T26	2		T2	1		T3	2
valid_sources[0x47]	6438	1			T26	3		T28	1		T30	1
valid_sources[0x48]	10593	1			T26	3		T8	5		T30	1
valid_sources[0x49]	7614	1			T26	1		T29	2		T9	2
valid_sources[0x4a]	6405	1			T6	11		T26	1		T2	2
valid_sources[0x4b]	10166	1			T26	1		T4	1		T8	1
valid_sources[0x4c]	15015	1			T28	1		T13	2		T14	18
valid_sources[0x4d]	18949	1			T26	4		T30	1		T12	3
valid_sources[0x4e]	6415	1			T4	1		T28	4		T30	1
valid_sources[0x4f]	6432	1			T10	17		T9	2		T36	2
valid_sources[0x50]	6671	1			T28	1		T10	5		T9	4
valid_sources[0x51]	7163	1			T26	1		T4	1		T10	27
valid_sources[0x52]	10487	1			T26	1		T30	1		T12	7
valid_sources[0x53]	5778	1			T5	1		T26	1		T2	1
valid_sources[0x54]	6331	1			T26	1		T10	6		T13	8
valid_sources[0x55]	6342	1			T26	2		T28	1		T30	2
valid_sources[0x56]	7061	1			T26	2		T4	1		T30	1
valid_sources[0x57]	6597	1			T4	1		T9	2		T12	2
valid_sources[0x58]	6249	1			T26	3		T2	2		T3	4
valid_sources[0x59]	7118	1			T3	1		T4	4		T28	4
valid_sources[0x5a]	6053	1			T28	1		T10	1		T11	3
valid_sources[0x5b]	8229	1			T5	1		T26	2		T10	7
valid_sources[0x5c]	10309	1			T2	2		T28	1		T8	11
valid_sources[0x5d]	6365	1			T2	1		T28	1		T9	4
valid_sources[0x5e]	6479	1			T26	1		T4	1		T29	2
valid_sources[0x5f]	10490	1			T26	1		T29	3		T10	1
valid_sources[0x60]	6347	1			T26	3		T13	3		T14	15
valid_sources[0x61]	8881	1			T26	1		T4	2		T10	1
valid_sources[0x62]	6534	1			T26	1		T2	1		T4	1
valid_sources[0x63]	6389	1			T26	1		T2	1		T29	2
valid_sources[0x64]	10793	1			T26	1		T30	1		T9	1
valid_sources[0x65]	6260	1			T26	3		T2	1		T4	1
valid_sources[0x66]	10199	1			T26	1		T3	2		T4	1
valid_sources[0x67]	7070	1			T5	1		T26	2		T2	5
valid_sources[0x68]	6258	1			T26	1		T10	28		T14	14
valid_sources[0x69]	6367	1			T26	3		T28	1		T8	2
valid_sources[0x6a]	8087	1			T2	1		T29	1		T12	3
valid_sources[0x6b]	6298	1			T3	2		T30	1		T12	2
valid_sources[0x6c]	6221	1			T4	1		T9	1		T14	14
valid_sources[0x6d]	5979	1			T5	4		T26	1		T2	2
valid_sources[0x6e]	6414	1			T26	4		T2	1		T3	2
valid_sources[0x6f]	8904	1			T5	1		T26	1		T4	1
valid_sources[0x70]	12724	1			T26	1		T4	1		T12	8
valid_sources[0x71]	9237	1			T26	1		T2	1		T10	5
valid_sources[0x72]	6205	1			T26	1		T28	1		T30	1
valid_sources[0x73]	6064	1			T9	6		T12	9		T14	9
valid_sources[0x74]	6696	1			T7	4		T26	1		T28	2
valid_sources[0x75]	6452	1			T5	3		T2	2		T28	2
valid_sources[0x76]	7391	1			T26	1		T29	1		T30	1
valid_sources[0x77]	6119	1			T5	2		T2	1		T28	5
valid_sources[0x78]	7516	1			T26	1		T28	1		T11	2
valid_sources[0x79]	6231	1			T1	45		T4	1		T10	6
valid_sources[0x7a]	6061	1			T26	1		T4	1		T30	1
valid_sources[0x7b]	6406	1			T26	4		T2	2		T28	1
valid_sources[0x7c]	19192	1			T30	1		T9	1		T14	10
valid_sources[0x7d]	6174	1			T2	2		T3	1		T4	2
valid_sources[0x7e]	6560	1			T26	2		T30	1		T10	13
valid_sources[0x7f]	5879	1			T3	3		T4	1		T28	2
valid_sources[0x80]	7211	1			T26	3		T28	1		T8	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

916252

1

T5

17

T6

27

T7

9

values[0x0]

all_enables

biggest_size

66440

1

T5

28

T6

31

T7

1

values[0x1]

all_enables

biggest_size

48724

1

T5

18

T6

19

T7

3