Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25394	1			T4	7		T8	9		T10	12
auto[PWRUP]	95	1			T38	4		T55	1		T33	1
auto[ONEST_0]	50	1			T38	1		T55	1		T195	1
auto[ONEST_021]	13	1			T196	1		T132	1		T197	1
auto[ONEST_1]	57	1			T20	1		T38	1		T55	1
auto[ONEST_DONE]	4	1			T195	1		T198	1		T199	1
auto[LP_0]	110	1			T20	1		T38	1		T33	2
auto[LP_021]	28	1			T38	1		T33	1		T195	1
auto[LP_1]	103	1			T20	2		T38	4		T55	1
auto[LP_EVAL]	63	1			T20	1		T39	1		T196	2
auto[LP_SLP]	455	1			T20	9		T38	6		T55	4
auto[LP_PWRUP]	22	1			T38	1		T33	1		T200	2
auto[NP_0]	144	1			T20	4		T38	2		T55	1
auto[NP_021]	32	1			T39	2		T195	1		T201	1
auto[NP_1]	140	1			T20	2		T38	1		T55	1
auto[NP_EVAL]	27	1			T38	1		T195	1		T201	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T38

1

T195

1

T190

1

min

24979

1

T4

7

T8

9

T10

12

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24988	1			T4	7		T8	9		T10	12
pow[0x1]	7	1			T201	1		T202	1		T203	1
pow[0x2]	16	1			T20	1		T38	1		T39	1
pow[0x3]	32	1			T55	1		T33	2		T201	1
pow[0x4]	64	1			T20	1		T38	1		T55	1
pow[0x5]	107	1			T20	1		T33	1		T39	3
pow[0x6]	193	1			T20	2		T38	5		T55	3
pow[0x7]	409	1			T20	6		T38	5		T55	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T20

1

T38

3

T55

5

min

24538

1

T4

7

T8

9

T10

12

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24538	1			T4	7		T8	9		T10	12
pow[0x5]	2	1			T20	1		T199	1		-	-
pow[0x6]	1	1			T204	1		-	-		-	-
pow[0x7]	4	1			T205	2		T206	1		T207	1
pow[0x8]	5	1			T38	1		T208	2		T207	1
pow[0x9]	5	1			T60	1		T209	1		T210	1
pow[0xa]	14	1			T63	1		T211	1		T212	2
pow[0xb]	37	1			T55	2		T39	1		T200	2
pow[0xc]	59	1			T20	2		T38	2		T200	1
pow[0xd]	132	1			T20	2		T38	1		T55	1
pow[0xe]	233	1			T20	2		T38	3		T55	6
pow[0xf]	527	1			T20	8		T38	5		T55	3