Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2159	1			T6	2		T3	2		T27	1
auto[PWRUP]	126	1			T20	1		T38	2		T55	1
auto[ONEST_0]	69	1			T20	1		T38	1		T39	1
auto[ONEST_021]	23	1			T20	1		T38	1		T39	1
auto[ONEST_1]	71	1			T38	2		T55	1		T33	1
auto[ONEST_DONE]	4	1			T337	1		T338	1		T66	1
auto[LP_0]	117	1			T20	2		T38	1		T55	1
auto[LP_021]	26	1			T55	1		T39	1		T195	1
auto[LP_1]	127	1			T20	1		T38	1		T55	1
auto[LP_EVAL]	47	1			T20	1		T38	1		T34	1
auto[LP_SLP]	471	1			T20	13		T38	12		T55	10
auto[LP_PWRUP]	27	1			T55	1		T33	2		T195	1
auto[NP_0]	211	1			T20	3		T38	2		T55	1
auto[NP_021]	48	1			T55	1		T58	1		T34	1
auto[NP_1]	224	1			T38	3		T55	1		T33	1
auto[NP_EVAL]	18	1			T34	1		T59	1		T63	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T195

1

T137

1

T339

1

min

1831

1

T6

2

T3

2

T27

1

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1840	1			T6	2		T3	2		T27	1
pow[0x1]	6	1			T39	1		T132	1		T338	1
pow[0x2]	17	1			T38	1		T201	2		T63	1
pow[0x3]	34	1			T55	1		T39	1		T195	1
pow[0x4]	51	1			T55	1		T196	2		T132	1
pow[0x5]	127	1			T38	4		T55	1		T33	3
pow[0x6]	228	1			T38	1		T55	2		T33	4
pow[0x7]	483	1			T20	6		T38	6		T55	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

182

1

T20

2

T38

4

T55

2

min

1264

1

T6

2

T3

2

T27

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1269	1			T6	2		T3	2		T27	1
pow[0x1]	13	1			T59	1		T142	1		T340	1
pow[0x2]	31	1			T58	2		T59	1		T189	1
pow[0x3]	47	1			T33	3		T35	2		T63	3
pow[0x4]	62	1			T59	3		T223	2		T63	1
pow[0x5]	1	1			T341	1		-	-		-	-
pow[0x6]	1	1			T342	1		-	-		-	-
pow[0x7]	2	1			T343	1		T344	1		-	-
pow[0x8]	7	1			T132	1		T138	1		T317	1
pow[0x9]	5	1			T339	1		T345	1		T346	1
pow[0xa]	15	1			T38	1		T33	1		T195	1
pow[0xb]	28	1			T200	1		T138	1		T339	1
pow[0xc]	61	1			T20	1		T201	1		T63	1
pow[0xd]	130	1			T38	1		T55	3		T33	2
pow[0xe]	272	1			T20	1		T38	5		T55	2
pow[0xf]	544	1			T20	6		T38	7		T55	7