Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T16,T31
1	Covered	T17,T20,T37

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T15,T16,T31
1	Covered	T15,T16,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T16,T20,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T16,T19,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T21
1	0	Covered	T15,T17,T18
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T15,T18,T20
1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T21
1	0	Covered	T16,T17,T20
1	1	Covered	T15,T16,T31

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T20
0	1	Covered	T15,T18,T20
1	0	Covered	T15,T18,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T20,T24,T41
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T41
0	1	Covered	T20,T24,T41
1	0	Covered	T20,T24,T41

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T15,T16,T20
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T17,T18,T19
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T15,T16,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T16,T19,T20
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T21
1	0	Covered	T15,T17,T18
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T15,T18,T20
1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T21
1	0	Covered	T16,T17,T19
1	1	Covered	T15,T16,T31

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T20
0	1	Covered	T15,T18,T20
1	0	Covered	T15,T18,T20

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T16,T18,T20
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T20

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T31
1	1	Covered	T15,T16,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T16,T18,T19
1	1	0	Covered	T16,T18,T19
1	1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T16,T18,T19
1	1	0	Covered	T16,T18,T19
1	1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T16,T18,T19
1	1	0	Covered	T16,T18,T19
1	1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T19

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T31
1	0	1	Covered	T16,T18,T20
1	1	0	Covered	T16,T18,T20
1	1	1	Covered	T16,T18,T20

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T20

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T31
1	1	Covered	T16,T18,T20

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T18
1	1	Covered	T15,T16,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T18
1	1	Covered	T15,T16,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T18
1	1	Covered	T15,T16,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T18
1	0	Covered	T15,T16,T18
1	1	Covered	T15,T16,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T18
1	1	Covered	T16,T18,T19

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T18
1	1	Covered	T16,T18,T19

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T15,T16,T18
1	1	Covered	T16,T18,T19

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T15,T16,T18
1	1	Covered	T16,T18,T20

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T20,T37
0	1	Covered	T15,T16,T17
0	0	Covered	T15,T16,T31

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T20,T24,T41

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T16,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T18,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T31
0	Covered	T15,T18,T20

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	28528376	28244207	0	0
gen_filter_match[0].MatchCheck00_A	28528376	8458987	0	0
gen_filter_match[0].MatchCheck01_A	28528376	2431730	0	0
gen_filter_match[0].MatchCheck10_A	28528376	2221613	0	0
gen_filter_match[0].MatchCheck11_A	28528376	15131877	0	0
gen_filter_match[1].MatchCheck00_A	28528376	9631719	0	0
gen_filter_match[1].MatchCheck01_A	28528376	1300126	0	0
gen_filter_match[1].MatchCheck10_A	28528376	1064034	0	0
gen_filter_match[1].MatchCheck11_A	28528376	16248328	0	0
gen_filter_match[2].MatchCheck00_A	28528376	10739129	0	0
gen_filter_match[2].MatchCheck01_A	28528376	586878	0	0
gen_filter_match[2].MatchCheck10_A	28528376	539736	0	0
gen_filter_match[2].MatchCheck11_A	28528376	16378464	0	0
gen_filter_match[3].MatchCheck00_A	28528376	10458926	0	0
gen_filter_match[3].MatchCheck01_A	28528376	113285	0	0
gen_filter_match[3].MatchCheck10_A	28528376	293009	0	0
gen_filter_match[3].MatchCheck11_A	28528376	17378987	0	0
gen_filter_match[4].MatchCheck00_A	28528376	10734214	0	0
gen_filter_match[4].MatchCheck01_A	28528376	26519	0	0
gen_filter_match[4].MatchCheck10_A	28528376	106253	0	0
gen_filter_match[4].MatchCheck11_A	28528376	17377221	0	0
gen_filter_match[5].MatchCheck00_A	28528376	10449952	0	0
gen_filter_match[5].MatchCheck01_A	28528376	65523	0	0
gen_filter_match[5].MatchCheck10_A	28528376	34035	0	0
gen_filter_match[5].MatchCheck11_A	28528376	17694697	0	0
gen_filter_match[6].MatchCheck00_A	28528376	10403028	0	0
gen_filter_match[6].MatchCheck01_A	28528376	101445	0	0
gen_filter_match[6].MatchCheck10_A	28528376	7840	0	0
gen_filter_match[6].MatchCheck11_A	28528376	17731894	0	0
gen_filter_match[7].MatchCheck00_A	28528376	10815373	0	0
gen_filter_match[7].MatchCheck01_A	28528376	180057	0	0
gen_filter_match[7].MatchCheck10_A	28528376	101111	0	0
gen_filter_match[7].MatchCheck11_A	28528376	17147666	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	28244207	0	0
T15	33280	33001	0	0
T16	33073	32989	0	0
T17	841	746	0	0
T18	33605	33517	0	0
T19	31824	31733	0	0
T20	93178	90552	0	0
T21	131424	131042	0	0
T22	33449	33355	0	0
T23	99247	99161	0	0
T31	63	7	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	8458987	0	0
T15	33280	12	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	31733	0	0
T20	93178	25394	0	0
T21	131424	15	0	0
T22	33449	4	0	0
T23	99247	3	0	0
T31	63	7	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	2431730	0	0
T15	33280	32989	0	0
T16	33073	0	0	0
T17	841	0	0	0
T18	33605	0	0	0
T19	31824	0	0	0
T20	93178	32217	0	0
T21	131424	32849	0	0
T22	33449	33351	0	0
T23	99247	0	0	0
T24	0	32751	0	0
T31	63	0	0	0
T41	0	32764	0	0
T53	0	33323	0	0
T103	0	1	0	0
T104	0	33241	0	0
T105	0	67126	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	2221613	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	32602	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	33251	0	0
T25	97702	0	0	0
T33	0	3	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T40	0	33624	0	0
T103	0	1	0	0
T106	0	33245	0	0
T107	0	33154	0	0
T108	0	34055	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	15131877	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	0	0	0
T20	93178	32941	0	0
T21	131424	65576	0	0
T22	33449	0	0	0
T23	99247	99156	0	0
T24	97820	0	0	0
T25	0	97624	0	0
T31	63	0	0	0
T38	0	1058	0	0
T41	0	33385	0	0
T42	0	31789	0	0
T106	0	32891	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	9631719	0	0
T15	33280	12	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	3	0	0
T20	93178	58335	0	0
T21	131424	131042	0	0
T22	33449	4	0	0
T23	99247	3	0	0
T31	63	7	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	1300126	0	0
T33	73730	0	0	0
T42	31881	31789	0	0
T99	927	0	0	0
T100	1131	0	0	0
T102	1170	0	0	0
T106	99169	32930	0	0
T107	66289	33040	0	0
T109	0	32848	0	0
T110	0	33268	0	0
T111	0	32558	0	0
T112	0	1	0	0
T113	0	33055	0	0
T114	0	32685	0	0
T115	0	33147	0	0
T116	32910	0	0	0
T117	63754	0	0	0
T118	44401	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	1064034	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	0	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T53	0	1	0	0
T54	0	34442	0	0
T104	0	32368	0	0
T112	0	1	0	0
T116	0	1	0	0
T119	0	32191	0	0
T120	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	16248328	0	0
T15	33280	32989	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	31730	0	0
T20	93178	32217	0	0
T21	131424	0	0	0
T22	33449	33351	0	0
T23	99247	99156	0	0
T25	0	97623	0	0
T31	63	0	0	0
T41	0	66149	0	0
T106	0	66136	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10739129	0	0
T15	33280	12	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	3	0	0
T20	93178	90552	0	0
T21	131424	66033	0	0
T22	33449	4	0	0
T23	99247	3	0	0
T31	63	7	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	586878	0	0
T63	63203	34489	0	0
T121	0	31757	0	0
T122	0	32460	0	0
T123	0	2	0	0
T124	0	33706	0	0
T125	0	1	0	0
T126	0	34191	0	0
T127	0	31687	0	0
T128	0	33134	0	0
T129	0	66454	0	0
T130	64637	0	0	0
T131	66153	0	0	0
T132	25169	0	0	0
T133	96093	0	0	0
T134	838	0	0	0
T135	4905	0	0	0
T136	98456	0	0	0
T137	40593	0	0	0
T138	23414	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	539736	0	0
T18	33605	1	0	0
T19	31824	31730	0	0
T20	93178	0	0	0
T21	131424	1	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T41	0	33385	0	0
T112	0	1	0	0
T116	0	2	0	0
T120	0	1	0	0
T139	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	16378464	0	0
T15	33280	32989	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	65008	0	0
T22	33449	33351	0	0
T23	99247	99156	0	0
T24	0	31762	0	0
T25	0	97623	0	0
T31	63	0	0	0
T42	0	31789	0	0
T106	0	33245	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10458926	0	0
T15	33280	12	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	31733	0	0
T20	93178	58335	0	0
T21	131424	32422	0	0
T22	33449	33355	0	0
T23	99247	3	0	0
T31	63	7	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	113285	0	0
T103	67288	1	0	0
T112	100604	1	0	0
T120	65157	0	0	0
T123	0	2	0	0
T139	64894	0	0	0
T140	0	1	0	0
T141	0	14712	0	0
T142	0	785	0	0
T143	0	1	0	0
T144	0	33927	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	56	0	0	0
T148	96828	0	0	0
T149	32717	0	0	0
T150	32700	0	0	0
T151	34597	0	0	0
T152	34827	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	293009	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	1	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T103	0	1	0	0
T109	0	2	0	0
T112	0	2	0	0
T119	0	32921	0	0
T120	0	1	0	0
T139	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	17378987	0	0
T15	33280	32989	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	0	0	0
T20	93178	32217	0	0
T21	131424	98619	0	0
T22	33449	0	0	0
T23	99247	99156	0	0
T25	0	97623	0	0
T31	63	0	0	0
T41	0	66149	0	0
T42	0	31789	0	0
T106	0	65821	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10734214	0	0
T15	33280	33001	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	3	0	0
T20	93178	90552	0	0
T21	131424	65786	0	0
T22	33449	33355	0	0
T23	99247	4	0	0
T31	63	7	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	26519	0	0
T34	38833	0	0	0
T109	97728	1	0	0
T110	98885	0	0	0
T119	98201	0	0	0
T123	0	1	0	0
T146	0	1	0	0
T153	0	1	0	0
T154	0	26507	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	1009	0	0	0
T161	101	0	0	0
T162	905	0	0	0
T163	91	0	0	0
T164	8645	0	0	0
T165	104	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	106253	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	2	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T50	0	34157	0	0
T58	0	7016	0	0
T103	0	1	0	0
T109	0	1	0	0
T112	0	1	0	0
T120	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	17377221	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	31730	0	0
T20	93178	0	0	0
T21	131424	65254	0	0
T22	33449	0	0	0
T23	99247	99155	0	0
T24	97820	97764	0	0
T25	0	97623	0	0
T31	63	0	0	0
T41	0	33385	0	0
T106	0	65821	0	0
T166	0	100113	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10449952	0	0
T15	33280	33001	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	3	0	0
T20	93178	26116	0	0
T21	131424	32422	0	0
T22	33449	4	0	0
T23	99247	4	0	0
T31	63	7	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	65523	0	0
T34	38833	0	0	0
T109	97728	32810	0	0
T110	98885	0	0	0
T119	98201	0	0	0
T128	0	32699	0	0
T140	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T160	1009	0	0	0
T161	101	0	0	0
T162	905	0	0	0
T163	91	0	0	0
T164	8645	0	0	0
T165	104	0	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	34035	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	3	0	0
T22	33449	1	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T53	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T116	0	1	0	0
T170	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	17694697	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	31730	0	0
T20	93178	64436	0	0
T21	131424	98617	0	0
T22	33449	33350	0	0
T23	99247	99155	0	0
T24	97820	0	0	0
T25	0	97623	0	0
T31	63	0	0	0
T41	0	32764	0	0
T106	0	33245	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10403028	0	0
T15	33280	33001	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	4	0	0
T19	31824	3	0	0
T20	93178	90552	0	0
T21	131424	131042	0	0
T22	33449	33355	0	0
T23	99247	4	0	0
T31	63	7	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	101445	0	0
T103	67288	1	0	0
T123	97725	31620	0	0
T124	99350	0	0	0
T140	0	1	0	0
T145	0	1	0	0
T155	0	1	0	0
T158	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	32346	0	0	0
T175	34106	0	0	0
T176	32968	0	0	0
T177	66269	0	0	0
T178	34957	0	0	0
T179	99423	0	0	0
T180	64395	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	7840	0	0
T18	33605	1	0	0
T19	31824	0	0	0
T20	93178	0	0	0
T21	131424	0	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T33	0	6	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T53	0	1	0	0
T103	0	1	0	0
T109	0	1	0	0
T112	0	1	0	0
T116	0	1	0	0
T170	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	17731894	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	31730	0	0
T20	93178	0	0	0
T21	131424	0	0	0
T22	33449	0	0	0
T23	99247	99155	0	0
T24	97820	31762	0	0
T25	0	97623	0	0
T31	63	0	0	0
T106	0	65821	0	0
T116	0	32854	0	0
T166	0	100113	0	0
T181	0	65322	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	10815373	0	0
T15	33280	33001	0	0
T16	33073	4	0	0
T17	841	746	0	0
T18	33605	5	0	0
T19	31824	31733	0	0
T20	93178	26116	0	0
T21	131424	65271	0	0
T22	33449	33355	0	0
T23	99247	4	0	0
T31	63	7	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	180057	0	0
T46	1580	0	0	0
T59	18659	0	0	0
T103	67288	1	0	0
T105	67196	2	0	0
T123	0	2	0	0
T125	0	2	0	0
T140	0	32453	0	0
T171	0	1	0	0
T177	0	33152	0	0
T179	0	1	0	0
T182	64886	1	0	0
T183	0	32619	0	0
T184	34103	0	0	0
T185	5741	0	0	0
T186	5536	0	0	0
T187	1173	0	0	0
T188	96431	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	101111	0	0
T21	131424	2	0	0
T22	33449	0	0	0
T23	99247	2	0	0
T24	97820	0	0	0
T25	97702	1	0	0
T33	0	4	0	0
T37	1179	0	0	0
T38	21091	0	0	0
T41	66227	0	0	0
T42	31881	0	0	0
T103	0	1	0	0
T105	0	2	0	0
T106	99169	0	0	0
T119	0	33004	0	0
T120	0	1	0	0
T139	0	1	0	0
T170	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28528376	17147666	0	0
T16	33073	32985	0	0
T17	841	0	0	0
T18	33605	33512	0	0
T19	31824	0	0	0
T20	93178	64436	0	0
T21	131424	65769	0	0
T22	33449	0	0	0
T23	99247	99155	0	0
T24	97820	64513	0	0
T25	0	97623	0	0
T31	63	0	0	0
T41	0	32764	0	0
T106	0	32930	0	0
T166	0	100113	0	0