Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6765	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2102	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1981	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2156	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1978	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2123	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2210	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2160	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2040	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2118	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2118	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2024	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2084	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2129	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1970	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2022	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2092	0	0
adc_en_ctl_rd_A	2147483647	1643	0	0
adc_fsm_rst_rd_A	2147483647	1538	0	0
adc_intr_ctl_rd_A	2147483647	1940	0	0
adc_lp_sample_ctl_rd_A	2147483647	1513	0	0
adc_pd_ctl_rd_A	2147483647	1992	0	0
adc_sample_ctl_rd_A	2147483647	1541	0	0
adc_wakeup_ctl_rd_A	2147483647	1561	0	0
intr_enable_rd_A	2147483647	2386	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6765	0	0
T1	6683	0	0	0
T2	49691	0	0	0
T3	28537	0	0	0
T4	15791	0	0	0
T5	5096	200	0	0
T6	12449	0	0	0
T7	9716	0	0	0
T10	0	2	0	0
T26	9884	167	0	0
T27	25664	0	0	0
T28	42533	482	0	0
T30	0	1	0	0
T34	0	4	0	0
T35	0	1	0	0
T57	0	269	0	0
T58	0	1	0	0
T59	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T9	65695	0	0	0
T10	401544	122	0	0
T11	14520	8	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	13	0	0
T35	0	10	0	0
T36	3902	0	0	0
T57	21858	6	0	0
T65	0	10	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	42	0	0
T189	0	17	0	0
T190	0	38	0	0
T191	0	30	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1981	0	0
T9	65695	0	0	0
T10	401544	149	0	0
T11	14520	8	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	8	0	0
T35	0	23	0	0
T36	3902	0	0	0
T57	21858	8	0	0
T65	0	21	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	30	0	0
T189	0	22	0	0
T190	0	24	0	0
T192	0	4	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2156	0	0
T9	65695	0	0	0
T10	401544	204	0	0
T11	14520	2	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	5	0	0
T35	0	23	0	0
T36	3902	0	0	0
T57	21858	50	0	0
T65	0	32	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	47	0	0
T189	0	4	0	0
T190	0	45	0	0
T192	0	6	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T9	65695	0	0	0
T10	401544	140	0	0
T11	14520	9	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	5	0	0
T35	0	16	0	0
T36	3902	0	0	0
T57	21858	33	0	0
T65	0	15	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	58	0	0
T189	0	16	0	0
T190	0	33	0	0
T192	0	13	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2123	0	0
T9	65695	0	0	0
T10	401544	226	0	0
T11	14520	34	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	10	0	0
T35	0	26	0	0
T36	3902	0	0	0
T57	21858	21	0	0
T65	0	24	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	29	0	0
T189	0	13	0	0
T190	0	41	0	0
T192	0	2	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2210	0	0
T9	65695	0	0	0
T10	401544	205	0	0
T11	14520	0	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	9	0	0
T35	0	18	0	0
T36	3902	0	0	0
T57	21858	14	0	0
T65	0	18	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	39	0	0
T189	0	22	0	0
T190	0	52	0	0
T191	0	24	0	0
T192	0	19	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2160	0	0
T9	65695	0	0	0
T10	401544	165	0	0
T11	14520	9	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T35	0	21	0	0
T36	3902	0	0	0
T57	21858	23	0	0
T65	0	24	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	53	0	0
T189	0	4	0	0
T190	0	58	0	0
T191	0	19	0	0
T192	0	13	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T9	65695	0	0	0
T10	401544	185	0	0
T11	14520	10	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	8	0	0
T35	0	20	0	0
T36	3902	0	0	0
T57	21858	30	0	0
T65	0	22	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	44	0	0
T189	0	14	0	0
T190	0	37	0	0
T192	0	19	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T9	65695	0	0	0
T10	401544	168	0	0
T11	14520	11	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	14	0	0
T35	0	16	0	0
T36	3902	0	0	0
T57	21858	23	0	0
T65	0	22	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	26	0	0
T189	0	27	0	0
T190	0	41	0	0
T192	0	11	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T9	65695	0	0	0
T10	401544	125	0	0
T11	14520	0	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T35	0	28	0	0
T36	3902	0	0	0
T57	21858	27	0	0
T65	0	19	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	38	0	0
T189	0	24	0	0
T190	0	43	0	0
T191	0	26	0	0
T192	0	11	0	0
T193	0	18	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2024	0	0
T9	65695	0	0	0
T10	401544	229	0	0
T11	14520	18	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	4	0	0
T35	0	18	0	0
T36	3902	0	0	0
T57	21858	17	0	0
T65	0	18	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	30	0	0
T189	0	14	0	0
T190	0	44	0	0
T192	0	5	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T9	65695	0	0	0
T10	401544	191	0	0
T11	14520	5	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	12	0	0
T35	0	29	0	0
T36	3902	0	0	0
T57	21858	57	0	0
T65	0	17	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	34	0	0
T189	0	28	0	0
T190	0	39	0	0
T192	0	10	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129	0	0
T9	65695	0	0	0
T10	401544	149	0	0
T11	14520	3	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	4	0	0
T35	0	13	0	0
T36	3902	0	0	0
T57	21858	18	0	0
T65	0	20	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	41	0	0
T189	0	27	0	0
T190	0	52	0	0
T192	0	1	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1970	0	0
T9	65695	0	0	0
T10	401544	170	0	0
T11	14520	24	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	8	0	0
T35	0	19	0	0
T36	3902	0	0	0
T57	21858	8	0	0
T65	0	17	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	32	0	0
T189	0	17	0	0
T190	0	36	0	0
T192	0	14	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2022	0	0
T9	65695	0	0	0
T10	401544	285	0	0
T11	14520	7	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	16	0	0
T35	0	19	0	0
T36	3902	0	0	0
T57	21858	17	0	0
T65	0	21	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	31	0	0
T189	0	34	0	0
T190	0	17	0	0
T192	0	11	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T9	65695	0	0	0
T10	401544	143	0	0
T11	14520	16	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	6	0	0
T35	0	13	0	0
T36	3902	0	0	0
T57	21858	20	0	0
T65	0	16	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	38	0	0
T189	0	25	0	0
T190	0	24	0	0
T192	0	3	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643	0	0
T9	65695	0	0	0
T10	401544	95	0	0
T11	14520	17	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	14	0	0
T35	0	28	0	0
T36	3902	0	0	0
T57	21858	5	0	0
T65	0	10	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	37	0	0
T189	0	18	0	0
T190	0	60	0	0
T192	0	10	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T9	65695	0	0	0
T10	401544	82	0	0
T11	14520	0	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T35	0	14	0	0
T36	3902	0	0	0
T57	21858	15	0	0
T65	0	21	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	32	0	0
T189	0	22	0	0
T190	0	33	0	0
T191	0	23	0	0
T192	0	9	0	0
T193	0	7	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T9	65695	0	0	0
T10	401544	66	0	0
T11	14520	1	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	4	0	0
T35	0	15	0	0
T36	3902	0	0	0
T57	21858	29	0	0
T65	0	27	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	43	0	0
T189	0	29	0	0
T190	0	46	0	0
T192	0	8	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T9	65695	0	0	0
T10	401544	72	0	0
T11	14520	0	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	4	0	0
T35	0	20	0	0
T36	3902	0	0	0
T57	21858	22	0	0
T65	0	31	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	27	0	0
T189	0	36	0	0
T190	0	43	0	0
T191	0	36	0	0
T192	0	13	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T9	65695	0	0	0
T10	401544	149	0	0
T11	14520	17	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	18	0	0
T35	0	28	0	0
T36	3902	0	0	0
T57	21858	12	0	0
T65	0	10	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	38	0	0
T189	0	19	0	0
T190	0	51	0	0
T191	0	26	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1541	0	0
T9	65695	0	0	0
T10	401544	90	0	0
T11	14520	3	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	4	0	0
T35	0	27	0	0
T36	3902	0	0	0
T57	21858	24	0	0
T65	0	17	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	31	0	0
T189	0	21	0	0
T190	0	41	0	0
T192	0	3	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T9	65695	0	0	0
T10	401544	82	0	0
T11	14520	4	0	0
T12	458336	0	0	0
T13	466699	0	0	0
T33	0	6	0	0
T35	0	34	0	0
T36	3902	0	0	0
T57	21858	34	0	0
T65	0	20	0	0
T67	12185	0	0	0
T72	261524	0	0	0
T73	116720	0	0	0
T142	0	33	0	0
T189	0	21	0	0
T190	0	41	0	0
T192	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2386	0	0
T1	6683	0	0	0
T2	49691	0	0	0
T3	28537	0	0	0
T4	15791	0	0	0
T7	9716	21	0	0
T8	54171	0	0	0
T10	0	85	0	0
T11	0	6	0	0
T15	0	55	0	0
T26	9884	0	0	0
T27	25664	0	0	0
T28	42533	0	0	0
T29	33043	0	0	0
T33	0	29	0	0
T35	0	45	0	0
T57	0	22	0	0
T67	0	9	0	0
T189	0	16	0	0
T194	0	7	0	0