Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1172648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1131498

1

T6

12

T7

18

T8

69

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2009517	1			T6	20		T7	19		T8	62
values[0x0]	146950	1			T6	9		T7	12		T8	25
values[0x1]	147679	1			T6	13		T7	9		T8	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	945185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1358961

1

T6

17

T7

20

T8

77

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13309	1			T8	1		T1	1		T4	2
valid_sources[0x01]	7510	1			T8	1		T1	1		T2	3
valid_sources[0x02]	7119	1			T8	1		T1	4		T4	3
valid_sources[0x03]	9415	1			T1	2		T4	3		T5	1
valid_sources[0x04]	7770	1			T1	1		T4	3		T27	1
valid_sources[0x05]	7890	1			T1	4		T2	1		T4	5
valid_sources[0x06]	8164	1			T1	5		T4	4		T5	1
valid_sources[0x07]	9827	1			T1	1		T4	9		T5	1
valid_sources[0x08]	12952	1			T1	2		T2	2		T4	2
valid_sources[0x09]	6882	1			T1	1		T4	2		T5	3
valid_sources[0x0a]	7901	1			T1	5		T2	2		T4	1
valid_sources[0x0b]	8270	1			T8	1		T1	3		T4	8
valid_sources[0x0c]	9264	1			T1	2		T4	3		T27	4
valid_sources[0x0d]	7109	1			T4	1		T5	3		T11	5
valid_sources[0x0e]	16489	1			T1	1		T4	2		T11	3
valid_sources[0x0f]	7647	1			T1	5		T4	2		T5	3
valid_sources[0x10]	12297	1			T1	5		T2	2		T4	5
valid_sources[0x11]	7685	1			T8	2		T1	1		T4	2
valid_sources[0x12]	9538	1			T1	4		T4	9		T27	1
valid_sources[0x13]	11822	1			T8	1		T1	3		T3	1
valid_sources[0x14]	6873	1			T8	1		T1	1		T2	1
valid_sources[0x15]	7098	1			T1	3		T4	2		T5	1
valid_sources[0x16]	7526	1			T1	2		T4	2		T5	2
valid_sources[0x17]	7016	1			T1	2		T2	1		T4	5
valid_sources[0x18]	7060	1			T4	2		T5	3		T11	5
valid_sources[0x19]	21990	1			T8	2		T1	1		T26	2
valid_sources[0x1a]	15928	1			T8	1		T1	1		T2	1
valid_sources[0x1b]	7538	1			T1	4		T2	2		T4	2
valid_sources[0x1c]	7224	1			T8	2		T1	2		T4	1
valid_sources[0x1d]	6633	1			T1	2		T26	1		T4	4
valid_sources[0x1e]	8401	1			T1	3		T4	2		T5	5
valid_sources[0x1f]	9221	1			T8	1		T1	3		T2	1
valid_sources[0x20]	9535	1			T1	1		T4	5		T27	3
valid_sources[0x21]	7371	1			T1	4		T4	1		T5	1
valid_sources[0x22]	11462	1			T1	5		T2	3		T4	2
valid_sources[0x23]	7260	1			T3	2		T4	5		T11	7
valid_sources[0x24]	6810	1			T1	1		T4	1		T11	4
valid_sources[0x25]	11342	1			T1	2		T4	5		T11	5
valid_sources[0x26]	6927	1			T6	27		T1	3		T3	12
valid_sources[0x27]	12305	1			T1	2		T2	1		T4	2
valid_sources[0x28]	7173	1			T2	1		T4	1		T5	3
valid_sources[0x29]	11441	1			T8	2		T1	5		T2	2
valid_sources[0x2a]	14031	1			T1	7		T4	2		T11	3
valid_sources[0x2b]	8100	1			T8	1		T4	5		T5	3
valid_sources[0x2c]	12104	1			T8	1		T1	1		T4	4
valid_sources[0x2d]	12356	1			T1	1		T2	2		T4	2
valid_sources[0x2e]	6841	1			T1	6		T4	5		T27	1
valid_sources[0x2f]	7107	1			T1	2		T3	35		T4	4
valid_sources[0x30]	7006	1			T1	3		T4	6		T5	3
valid_sources[0x31]	7822	1			T8	2		T1	5		T4	4
valid_sources[0x32]	8252	1			T1	5		T4	5		T11	10
valid_sources[0x33]	9372	1			T8	1		T1	1		T2	3
valid_sources[0x34]	7151	1			T8	1		T4	5		T11	10
valid_sources[0x35]	11125	1			T1	1		T4	2		T5	1
valid_sources[0x36]	6621	1			T1	5		T26	1		T3	5
valid_sources[0x37]	12621	1			T8	1		T1	7		T26	1
valid_sources[0x38]	7156	1			T8	1		T1	2		T4	2
valid_sources[0x39]	11478	1			T4	6		T5	1		T11	4
valid_sources[0x3a]	8639	1			T1	3		T2	1		T4	2
valid_sources[0x3b]	7230	1			T1	9		T4	1		T5	4
valid_sources[0x3c]	8135	1			T1	4		T2	1		T4	4
valid_sources[0x3d]	10663	1			T1	1		T3	1		T4	2
valid_sources[0x3e]	7992	1			T1	5		T4	4		T11	9
valid_sources[0x3f]	6567	1			T4	4		T5	1		T11	6
valid_sources[0x40]	7040	1			T1	4		T4	2		T5	2
valid_sources[0x41]	11026	1			T1	2		T3	9		T4	9
valid_sources[0x42]	12315	1			T1	1		T4	1		T27	1
valid_sources[0x43]	10701	1			T1	3		T4	2		T5	3
valid_sources[0x44]	7520	1			T8	1		T1	9		T26	1
valid_sources[0x45]	6873	1			T8	1		T1	3		T2	2
valid_sources[0x46]	7008	1			T1	2		T4	1		T5	2
valid_sources[0x47]	6925	1			T1	2		T3	5		T4	3
valid_sources[0x48]	6979	1			T1	1		T26	1		T4	4
valid_sources[0x49]	7443	1			T8	1		T1	2		T4	3
valid_sources[0x4a]	7287	1			T2	1		T4	2		T5	2
valid_sources[0x4b]	7462	1			T8	1		T1	3		T4	4
valid_sources[0x4c]	7080	1			T1	2		T4	1		T9	15
valid_sources[0x4d]	9526	1			T1	1		T4	3		T27	1
valid_sources[0x4e]	6989	1			T1	3		T2	1		T4	1
valid_sources[0x4f]	21861	1			T8	1		T1	1		T4	5
valid_sources[0x50]	11000	1			T8	1		T1	4		T4	2
valid_sources[0x51]	6951	1			T1	2		T4	3		T27	1
valid_sources[0x52]	11211	1			T1	4		T4	1		T5	2
valid_sources[0x53]	7172	1			T1	3		T27	2		T9	3
valid_sources[0x54]	7225	1			T8	1		T1	1		T4	2
valid_sources[0x55]	12398	1			T8	1		T1	5		T4	5
valid_sources[0x56]	8032	1			T1	3		T4	2		T5	4
valid_sources[0x57]	7736	1			T8	1		T1	3		T4	3
valid_sources[0x58]	8121	1			T1	3		T4	6		T5	2
valid_sources[0x59]	7046	1			T1	10		T2	1		T4	3
valid_sources[0x5a]	12404	1			T1	2		T2	1		T4	2
valid_sources[0x5b]	7213	1			T8	1		T1	5		T4	2
valid_sources[0x5c]	7288	1			T8	2		T1	1		T4	5
valid_sources[0x5d]	6733	1			T8	1		T1	8		T2	2
valid_sources[0x5e]	8004	1			T1	4		T4	2		T27	1
valid_sources[0x5f]	6824	1			T1	5		T4	3		T27	2
valid_sources[0x60]	11153	1			T1	3		T4	4		T11	6
valid_sources[0x61]	7645	1			T1	3		T4	4		T5	2
valid_sources[0x62]	7520	1			T1	3		T26	1		T4	4
valid_sources[0x63]	7124	1			T1	4		T2	2		T27	2
valid_sources[0x64]	6940	1			T1	5		T4	2		T5	2
valid_sources[0x65]	11015	1			T8	1		T2	2		T4	1
valid_sources[0x66]	7386	1			T1	6		T4	5		T5	1
valid_sources[0x67]	11779	1			T4	4		T11	9		T12	7
valid_sources[0x68]	11585	1			T8	2		T1	3		T3	9
valid_sources[0x69]	6935	1			T1	8		T4	4		T5	1
valid_sources[0x6a]	7142	1			T1	3		T4	1		T5	1
valid_sources[0x6b]	7271	1			T1	7		T4	9		T5	1
valid_sources[0x6c]	6811	1			T6	3		T8	1		T1	1
valid_sources[0x6d]	7223	1			T1	2		T4	1		T27	2
valid_sources[0x6e]	10953	1			T1	5		T4	7		T27	1
valid_sources[0x6f]	13732	1			T1	3		T4	2		T11	8
valid_sources[0x70]	9151	1			T2	1		T4	3		T5	1
valid_sources[0x71]	7583	1			T3	5		T4	1		T5	1
valid_sources[0x72]	7116	1			T8	1		T1	3		T2	2
valid_sources[0x73]	6886	1			T8	1		T1	9		T2	1
valid_sources[0x74]	6770	1			T1	3		T3	9		T4	3
valid_sources[0x75]	7366	1			T1	2		T2	2		T4	1
valid_sources[0x76]	7950	1			T8	1		T1	7		T4	1
valid_sources[0x77]	7885	1			T1	1		T4	5		T5	3
valid_sources[0x78]	6997	1			T1	9		T4	3		T27	3
valid_sources[0x79]	6948	1			T1	6		T4	6		T5	1
valid_sources[0x7a]	11063	1			T1	4		T4	2		T5	5
valid_sources[0x7b]	10118	1			T1	9		T4	2		T27	1
valid_sources[0x7c]	11342	1			T7	40		T2	1		T27	2
valid_sources[0x7d]	6947	1			T1	5		T5	3		T11	8
valid_sources[0x7e]	10926	1			T8	1		T1	1		T2	1
valid_sources[0x7f]	8470	1			T8	1		T1	6		T4	5
valid_sources[0x80]	11507	1			T8	1		T1	2		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1001655

1

T6

9

T7

12

T8

33

values[0x0]

all_enables

biggest_size

75034

1

T6

1

T7

4

T8

21

values[0x1]

all_enables

biggest_size

54809

1

T6

2

T7

2

T8

15