Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30657	1			T1	5		T4	51		T5	37
auto[PWRUP]	122	1			T13	1		T18	2		T21	3
auto[ONEST_0]	83	1			T102	1		T116	2		T144	1
auto[ONEST_021]	19	1			T21	1		T159	1		T207	3
auto[ONEST_1]	76	1			T18	2		T21	3		T22	1
auto[ONEST_DONE]	5	1			T208	1		T209	1		T210	1
auto[LP_0]	144	1			T18	1		T21	5		T22	2
auto[LP_021]	31	1			T18	2		T22	1		T144	2
auto[LP_1]	148	1			T13	1		T18	2		T21	5
auto[LP_EVAL]	79	1			T13	2		T18	1		T21	1
auto[LP_SLP]	517	1			T18	9		T21	14		T22	3
auto[LP_PWRUP]	23	1			T18	2		T21	2		T102	1
auto[NP_0]	158	1			T18	3		T21	7		T22	1
auto[NP_021]	31	1			T22	1		T41	1		T211	1
auto[NP_1]	146	1			T18	3		T21	2		T22	5
auto[NP_EVAL]	26	1			T18	1		T21	1		T43	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T21

1

T212

1

T213

1

min

30160

1

T1

5

T4

51

T5

37

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30170	1			T1	5		T4	51		T5	37
pow[0x1]	7	1			T18	1		T21	1		T41	1
pow[0x2]	13	1			T214	1		T209	1		T215	1
pow[0x3]	42	1			T21	1		T41	1		T102	1
pow[0x4]	62	1			T18	2		T21	2		T43	1
pow[0x5]	124	1			T13	1		T18	1		T21	6
pow[0x6]	269	1			T18	6		T21	9		T22	5
pow[0x7]	517	1			T13	2		T18	9		T21	14

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

211

1

T18

4

T21

6

T22

2

min

29660

1

T1

5

T4

51

T5

37

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29660	1			T1	5		T4	51		T5	37
pow[0x6]	1	1			T216	1		-	-		-	-
pow[0x7]	2	1			T211	1		T213	1		-	-
pow[0x8]	3	1			T209	1		T217	1		T218	1
pow[0x9]	6	1			T21	1		T102	1		T219	1
pow[0xa]	22	1			T144	2		T211	1		T174	1
pow[0xb]	34	1			T21	2		T41	2		T43	1
pow[0xc]	70	1			T21	3		T22	1		T41	1
pow[0xd]	161	1			T18	4		T21	4		T22	1
pow[0xe]	310	1			T13	1		T18	2		T21	20
pow[0xf]	594	1			T18	8		T21	15		T22	6