Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2273	1			T8	2		T1	10		T2	2
auto[PWRUP]	126	1			T18	3		T22	1		T41	2
auto[ONEST_0]	65	1			T18	1		T21	4		T22	1
auto[ONEST_021]	18	1			T41	1		T211	1		T160	1
auto[ONEST_1]	94	1			T21	1		T41	4		T43	1
auto[ONEST_DONE]	1	1			T358	1		-	-		-	-
auto[LP_0]	121	1			T18	3		T21	4		T41	3
auto[LP_021]	41	1			T13	1		T21	1		T211	1
auto[LP_1]	139	1			T18	2		T21	3		T41	1
auto[LP_EVAL]	61	1			T13	1		T21	1		T102	1
auto[LP_SLP]	555	1			T18	9		T21	10		T22	8
auto[LP_PWRUP]	36	1			T21	2		T102	1		T43	1
auto[NP_0]	227	1			T13	2		T18	1		T21	3
auto[NP_021]	59	1			T13	1		T21	2		T41	3
auto[NP_1]	245	1			T13	1		T18	3		T21	4
auto[NP_EVAL]	42	1			T13	1		T21	1		T116	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T41

1

T359

1

T360

1

min

1960

1

T8

2

T1

10

T2

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1971	1			T8	2		T1	10		T2	2
pow[0x1]	7	1			T43	1		T361	1		T362	1
pow[0x2]	14	1			T211	1		T159	1		T207	1
pow[0x3]	32	1			T18	1		T102	1		T358	1
pow[0x4]	71	1			T18	1		T21	1		T22	1
pow[0x5]	138	1			T18	3		T21	4		T22	2
pow[0x6]	301	1			T13	1		T18	5		T21	8
pow[0x7]	548	1			T13	2		T18	8		T21	14

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T21

4

T22

2

T41

2

min

1327

1

T8

2

T1

10

T2

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1330	1			T8	2		T1	10		T2	2
pow[0x1]	32	1			T102	1		T195	3		T277	1
pow[0x2]	33	1			T13	1		T41	3		T224	1
pow[0x3]	35	1			T102	2		T225	1		T160	1
pow[0x4]	43	1			T102	1		T197	3		T130	3
pow[0x5]	1	1			T213	1		-	-		-	-
pow[0x6]	1	1			T21	1		-	-		-	-
pow[0x7]	2	1			T363	1		T364	1		-	-
pow[0x8]	4	1			T21	1		T41	1		T365	1
pow[0x9]	7	1			T361	2		T366	1		T367	1
pow[0xa]	20	1			T207	1		T212	2		T368	1
pow[0xb]	41	1			T18	1		T21	1		T358	1
pow[0xc]	79	1			T18	2		T21	1		T22	3
pow[0xd]	139	1			T18	3		T21	2		T41	3
pow[0xe]	300	1			T18	6		T21	10		T22	3
pow[0xf]	595	1			T13	2		T18	8		T21	11