Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T18,T19

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T20,T24,T102
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T107
0	1	Covered	T20,T24,T107
1	0	Covered	T20,T24,T102

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T17
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T20
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T17
0	1	Covered	T13,T16,T17
1	0	Covered	T13,T16,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T20,T24,T58
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T58
0	1	Covered	T20,T24,T58
1	0	Covered	T20,T24,T58

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T20
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T58
0	1	Covered	T17,T20,T58
1	0	Covered	T13,T17,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T24
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T24
0	1	Covered	T16,T24,T58
1	0	Covered	T13,T16,T24

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T24
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T24
0	1	Covered	T13,T17,T24
1	0	Covered	T13,T17,T24

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T17
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T23
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T20
0	1	Covered	T16,T17,T20
1	0	Covered	T13,T16,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T58
1	0	Covered	T13,T16,T18
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T20,T58,T102
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T58,T43
0	1	Covered	T20,T58,T43
1	0	Covered	T20,T58,T102

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T24
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T24
0	1	Covered	T13,T16,T24
1	0	Covered	T13,T16,T24

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T20,T24,T58
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T58
0	1	Covered	T20,T24,T58
1	0	Covered	T20,T24,T58

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T20
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T58
0	1	Covered	T17,T20,T58
1	0	Covered	T13,T17,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T24
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T24
0	1	Covered	T16,T24,T58
1	0	Covered	T13,T16,T24

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T24
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T24
0	1	Covered	T13,T17,T24
1	0	Covered	T13,T17,T24

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T16,T17
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T23
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T20
0	1	Covered	T16,T17,T20
1	0	Covered	T13,T16,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T58
1	0	Covered	T13,T16,T18
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T14,T15,T16
1	1	0	Covered	T14,T15,T23
1	1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T14,T15,T16
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T14,T15,T16
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T18,T19
0	1	Covered	T13,T14,T15
0	0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T20,T24,T102

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T20,T58,T102

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T24

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T20,T24,T58

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T20,T24,T58

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T17,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T17,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T24

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T24

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T17,T24

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T17,T24

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T16,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32404515	32089377	0	0
gen_filter_match[0].MatchCheck00_A	32404515	9246072	0	0
gen_filter_match[0].MatchCheck01_A	32404515	2558652	0	0
gen_filter_match[0].MatchCheck10_A	32404515	2562584	0	0
gen_filter_match[0].MatchCheck11_A	32404515	17722069	0	0
gen_filter_match[1].MatchCheck00_A	32404515	11633792	0	0
gen_filter_match[1].MatchCheck01_A	32404515	812981	0	0
gen_filter_match[1].MatchCheck10_A	32404515	1534754	0	0
gen_filter_match[1].MatchCheck11_A	32404515	18107850	0	0
gen_filter_match[2].MatchCheck00_A	32404515	11782262	0	0
gen_filter_match[2].MatchCheck01_A	32404515	571891	0	0
gen_filter_match[2].MatchCheck10_A	32404515	428140	0	0
gen_filter_match[2].MatchCheck11_A	32404515	19307084	0	0
gen_filter_match[3].MatchCheck00_A	32404515	11472862	0	0
gen_filter_match[3].MatchCheck01_A	32404515	182704	0	0
gen_filter_match[3].MatchCheck10_A	32404515	398269	0	0
gen_filter_match[3].MatchCheck11_A	32404515	20035542	0	0
gen_filter_match[4].MatchCheck00_A	32404515	12149815	0	0
gen_filter_match[4].MatchCheck01_A	32404515	99832	0	0
gen_filter_match[4].MatchCheck10_A	32404515	32969	0	0
gen_filter_match[4].MatchCheck11_A	32404515	19806761	0	0
gen_filter_match[5].MatchCheck00_A	32404515	12638392	0	0
gen_filter_match[5].MatchCheck01_A	32404515	32320	0	0
gen_filter_match[5].MatchCheck10_A	32404515	32348	0	0
gen_filter_match[5].MatchCheck11_A	32404515	19386317	0	0
gen_filter_match[6].MatchCheck00_A	32404515	11940797	0	0
gen_filter_match[6].MatchCheck01_A	32404515	114893	0	0
gen_filter_match[6].MatchCheck10_A	32404515	89435	0	0
gen_filter_match[6].MatchCheck11_A	32404515	19944252	0	0
gen_filter_match[7].MatchCheck00_A	32404515	12016314	0	0
gen_filter_match[7].MatchCheck01_A	32404515	153219	0	0
gen_filter_match[7].MatchCheck10_A	32404515	167813	0	0
gen_filter_match[7].MatchCheck11_A	32404515	19752031	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	32089377	0	0
T13	12207	11534	0	0
T14	34089	34020	0	0
T15	63477	63402	0	0
T16	34240	34149	0	0
T17	32598	32543	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	9246072	0	0
T13	12207	1583	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	4	0	0
T18	25356	21570	0	0
T19	904	830	0	0
T20	33583	4	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	2558652	0	0
T38	67542	33088	0	0
T41	55138	0	0	0
T43	120273	0	0	0
T58	32750	32677	0	0
T102	44777	0	0	0
T104	1198	0	0	0
T107	33462	33396	0	0
T108	0	32406	0	0
T109	0	66063	0	0
T110	0	34027	0	0
T111	0	33505	0	0
T112	0	33457	0	0
T113	0	31933	0	0
T114	0	32224	0	0
T115	97329	0	0	0
T116	25290	0	0	0
T117	8542	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	2562584	0	0
T13	12207	9257	0	0
T14	34089	0	0	0
T15	63477	0	0	0
T16	34240	0	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T24	0	33014	0	0
T29	91	0	0	0
T30	89	0	0	0
T56	0	32232	0	0
T108	0	1	0	0
T111	0	32630	0	0
T118	0	32670	0	0
T119	0	32759	0	0
T120	0	1	0	0
T121	0	33402	0	0
T122	0	31783	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	17722069	0	0
T13	12207	694	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	32539	0	0
T18	25356	696	0	0
T19	904	0	0	0
T20	33583	33485	0	0
T21	0	775	0	0
T22	0	67	0	0
T23	0	98179	0	0
T29	91	0	0	0
T30	89	0	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	11633792	0	0
T13	12207	2277	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	4	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	812981	0	0
T16	34240	34145	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T21	47538	0	0	0
T22	17975	0	0	0
T23	98254	0	0	0
T29	91	0	0	0
T30	89	0	0	0
T110	0	32926	0	0
T123	0	31974	0	0
T124	0	31732	0	0
T125	0	34156	0	0
T126	0	31913	0	0
T127	0	32802	0	0
T128	0	32629	0	0
T129	0	32885	0	0
T130	0	5436	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	1534754	0	0
T17	32598	32539	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T21	47538	0	0	0
T22	17975	0	0	0
T23	98254	0	0	0
T24	65267	0	0	0
T25	99663	0	0	0
T30	89	0	0	0
T38	0	34376	0	0
T51	0	33135	0	0
T56	0	33911	0	0
T102	0	15063	0	0
T108	0	2	0	0
T120	0	2	0	0
T131	0	32981	0	0
T132	0	33080	0	0
T133	0	33140	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	18107850	0	0
T13	12207	9257	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	0	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T23	0	98179	0	0
T24	0	33014	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T43	0	32626	0	0
T58	0	32677	0	0
T59	0	34267	0	0
T102	0	430	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	11782262	0	0
T13	12207	11534	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	32543	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	571891	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	32248	0	0
T131	33065	0	0	0
T134	97188	32867	0	0
T135	0	31752	0	0
T136	0	33842	0	0
T137	0	33067	0	0
T138	0	31730	0	0
T139	0	33276	0	0
T140	0	1	0	0
T141	0	32374	0	0
T142	0	33680	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	428140	0	0
T120	33286	2	0	0
T148	64500	31822	0	0
T149	97526	32417	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	32918	0	0
T153	0	1	0	0
T154	0	33678	0	0
T155	0	33673	0	0
T156	0	1	0	0
T157	70	0	0	0
T158	32056	0	0	0
T159	20628	0	0	0
T160	6268	0	0	0
T161	33876	0	0	0
T162	33309	0	0	0
T163	98944	0	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	19307084	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T21	47538	0	0	0
T23	0	98179	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T43	0	32626	0	0
T59	0	34267	0	0
T102	0	15063	0	0
T108	0	32362	0	0
T115	0	97239	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	11472862	0	0
T13	12207	11534	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	32543	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	4	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	182704	0	0
T121	33458	0	0	0
T138	0	32218	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0
T149	97526	0	0	0
T151	0	1	0	0
T160	6268	1725	0	0
T161	33876	0	0	0
T162	33309	0	0	0
T163	98944	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	33694	0	0
T167	0	32956	0	0
T168	34240	0	0	0
T169	8853	0	0	0
T170	105	0	0	0
T171	24573	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	398269	0	0
T39	65373	32947	0	0
T40	111987	0	0	0
T52	5734	0	0	0
T53	900	0	0	0
T54	65257	0	0	0
T55	32969	0	0	0
T56	99251	0	0	0
T57	5204	0	0	0
T120	0	2	0	0
T132	100208	0	0	0
T133	0	32716	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	0	32019	0	0
T156	0	1	0	0
T158	0	31962	0	0
T172	0	47589	0	0
T173	0	1	0	0
T174	22324	0	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	20035542	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	33485	0	0
T21	47538	0	0	0
T23	0	98179	0	0
T24	0	33014	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T41	0	31547	0	0
T59	0	34267	0	0
T102	0	430	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	12149815	0	0
T13	12207	2277	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	4	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	99832	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	1	0	0
T131	33065	0	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T165	0	1	0	0
T175	66422	33521	0	0
T176	0	32519	0	0
T177	0	1	0	0
T178	0	33786	0	0
T179	0	2	0	0
T180	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	32969	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	2	0	0
T120	0	1	0	0
T131	33065	0	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0
T181	100180	1	0	0
T182	0	1	0	0
T183	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	19806761	0	0
T13	12207	9257	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	32539	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T23	0	98179	0	0
T24	0	32184	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T43	0	33220	0	0
T59	0	34267	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	12638392	0	0
T13	12207	2277	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	34149	0	0
T17	32598	4	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	32320	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	1	0	0
T131	33065	0	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T164	98443	1	0	0
T177	0	1	0	0
T184	0	32306	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	2	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	32348	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	2	0	0
T120	0	1	0	0
T131	33065	0	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	2	0	0
T156	0	1	0	0
T173	0	1	0	0
T181	100180	1	0	0
T182	0	1	0	0
T191	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	19386317	0	0
T13	12207	9257	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	0	0	0
T17	32598	32539	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T23	0	98179	0	0
T24	0	65198	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T41	0	31547	0	0
T59	0	34267	0	0
T102	0	15063	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	11940797	0	0
T13	12207	11534	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	4	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	4	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	114893	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	2	0	0
T131	33065	0	0	0
T139	0	1	0	0
T140	0	1	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T148	64500	32579	0	0
T164	0	1	0	0
T165	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	23451	0	0
T194	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	89435	0	0
T44	85	0	0	0
T103	9908	0	0	0
T108	97089	2	0	0
T120	0	1	0	0
T131	33065	1	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T145	715	0	0	0
T146	32865	0	0	0
T147	33326	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T158	0	1	0	0
T181	100180	1	0	0
T182	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	19944252	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	32539	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	33485	0	0
T21	47538	0	0	0
T23	0	98179	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T58	0	32677	0	0
T59	0	34267	0	0
T102	0	15493	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	12016314	0	0
T13	12207	2277	0	0
T14	34089	4	0	0
T15	63477	4	0	0
T16	34240	4	0	0
T17	32598	32543	0	0
T18	25356	22266	0	0
T19	904	830	0	0
T20	33583	33489	0	0
T29	91	7	0	0
T30	89	11	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	153219	0	0
T38	67542	0	0	0
T43	120273	33220	0	0
T103	9908	0	0	0
T108	97089	2	0	0
T115	97329	0	0	0
T116	25290	0	0	0
T117	8542	0	0	0
T131	33065	0	0	0
T139	0	1	0	0
T140	0	33386	0	0
T143	1196	0	0	0
T144	29793	0	0	0
T151	0	1	0	0
T185	0	1	0	0
T197	0	14866	0	0
T198	0	39632	0	0
T199	0	1	0	0
T200	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	167813	0	0
T13	12207	2	0	0
T14	34089	0	0	0
T15	63477	0	0	0
T16	34240	0	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T29	91	0	0	0
T30	89	0	0	0
T108	0	1	0	0
T120	0	1	0	0
T133	0	32783	0	0
T150	0	1	0	0
T151	0	1	0	0
T181	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32404515	19752031	0	0
T13	12207	9255	0	0
T14	34089	34016	0	0
T15	63477	63398	0	0
T16	34240	34145	0	0
T17	32598	0	0	0
T18	25356	0	0	0
T19	904	0	0	0
T20	33583	0	0	0
T23	0	98179	0	0
T24	0	65198	0	0
T25	0	99588	0	0
T29	91	0	0	0
T30	89	0	0	0
T41	0	31547	0	0
T58	0	32677	0	0
T102	0	15493	0	0