Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6802	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2098	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2016	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2099	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2045	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2150	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2062	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2277	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2025	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2086	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2115	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2213	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1988	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2281	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2063	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2260	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2167	0	0
adc_en_ctl_rd_A	2147483647	1826	0	0
adc_fsm_rst_rd_A	2147483647	1715	0	0
adc_intr_ctl_rd_A	2147483647	1648	0	0
adc_lp_sample_ctl_rd_A	2147483647	1686	0	0
adc_pd_ctl_rd_A	2147483647	1847	0	0
adc_sample_ctl_rd_A	2147483647	1804	0	0
adc_wakeup_ctl_rd_A	2147483647	1786	0	0
intr_enable_rd_A	2147483647	2200	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6802	0	0
T12	87049	0	0	0
T35	28653	581	0	0
T61	6113	257	0	0
T62	44726	462	0	0
T63	0	134	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	203	0	0
T69	43650	0	0	0
T70	19374	0	0	0
T73	0	362	0	0
T77	14479	0	0	0
T78	42427	0	0	0
T79	131749	0	0	0
T80	11509	0	0	0
T203	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T1	230955	66	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	47	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	31	0	0
T35	0	11	0	0
T60	0	71	0	0
T69	0	5	0	0
T71	0	12	0	0
T81	0	4	0	0
T82	0	6	0	0
T204	0	1	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2016	0	0
T1	230955	39	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	60	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	17	0	0
T35	0	15	0	0
T60	0	104	0	0
T66	0	88	0	0
T69	0	1	0	0
T71	0	9	0	0
T82	0	22	0	0
T204	0	7	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2099	0	0
T1	230955	58	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	51	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	28	0	0
T35	0	8	0	0
T60	0	161	0	0
T66	0	105	0	0
T69	0	11	0	0
T81	0	3	0	0
T82	0	35	0	0
T204	0	4	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2045	0	0
T1	230955	24	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	52	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	8	0	0
T35	0	14	0	0
T60	0	85	0	0
T66	0	62	0	0
T69	0	16	0	0
T71	0	2	0	0
T82	0	13	0	0
T97	0	8	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2150	0	0
T1	230955	38	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	43	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	36	0	0
T35	0	14	0	0
T60	0	64	0	0
T66	0	102	0	0
T69	0	2	0	0
T71	0	18	0	0
T81	0	9	0	0
T82	0	7	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2062	0	0
T1	230955	37	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	62	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	16	0	0
T35	0	9	0	0
T60	0	90	0	0
T66	0	89	0	0
T69	0	9	0	0
T71	0	4	0	0
T81	0	4	0	0
T82	0	20	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2277	0	0
T1	230955	53	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	68	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	40	0	0
T35	0	18	0	0
T60	0	144	0	0
T66	0	129	0	0
T69	0	7	0	0
T82	0	9	0	0
T97	0	7	0	0
T204	0	3	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2025	0	0
T1	230955	32	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	52	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	17	0	0
T35	0	10	0	0
T60	0	80	0	0
T69	0	12	0	0
T71	0	8	0	0
T81	0	13	0	0
T82	0	17	0	0
T204	0	3	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086	0	0
T1	230955	25	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	41	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	40	0	0
T35	0	7	0	0
T60	0	134	0	0
T69	0	10	0	0
T71	0	7	0	0
T81	0	9	0	0
T82	0	7	0	0
T204	0	6	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T1	230955	41	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	61	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	78	0	0
T35	0	9	0	0
T60	0	81	0	0
T66	0	84	0	0
T69	0	4	0	0
T81	0	8	0	0
T82	0	7	0	0
T204	0	3	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T1	230955	67	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	30	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	77	0	0
T35	0	11	0	0
T60	0	107	0	0
T66	0	123	0	0
T69	0	8	0	0
T71	0	4	0	0
T81	0	24	0	0
T82	0	6	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T1	230955	55	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	56	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	51	0	0
T35	0	3	0	0
T60	0	133	0	0
T66	0	76	0	0
T69	0	10	0	0
T71	0	1	0	0
T82	0	2	0	0
T97	0	20	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2281	0	0
T1	230955	52	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	58	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	79	0	0
T35	0	25	0	0
T60	0	130	0	0
T66	0	72	0	0
T69	0	7	0	0
T71	0	13	0	0
T82	0	10	0	0
T204	0	5	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T1	230955	35	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	20	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	24	0	0
T35	0	40	0	0
T60	0	108	0	0
T69	0	12	0	0
T71	0	9	0	0
T81	0	10	0	0
T82	0	9	0	0
T204	0	5	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2260	0	0
T1	230955	59	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	52	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	35	0	0
T35	0	33	0	0
T60	0	88	0	0
T66	0	125	0	0
T69	0	10	0	0
T71	0	14	0	0
T81	0	7	0	0
T97	0	25	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2167	0	0
T1	230955	68	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	44	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	35	0	0
T35	0	10	0	0
T60	0	112	0	0
T66	0	81	0	0
T69	0	2	0	0
T82	0	14	0	0
T97	0	3	0	0
T204	0	9	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T1	230955	21	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	37	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	35	0	0
T35	0	13	0	0
T60	0	62	0	0
T69	0	17	0	0
T71	0	6	0	0
T81	0	5	0	0
T82	0	2	0	0
T204	0	5	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1715	0	0
T1	230955	28	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	20	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	33	0	0
T35	0	28	0	0
T60	0	45	0	0
T66	0	42	0	0
T69	0	5	0	0
T71	0	5	0	0
T97	0	11	0	0
T204	0	3	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T1	230955	20	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	4	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	28	0	0
T35	0	21	0	0
T60	0	39	0	0
T66	0	33	0	0
T69	0	7	0	0
T81	0	3	0	0
T82	0	11	0	0
T204	0	1	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1686	0	0
T1	230955	15	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	9	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	31	0	0
T35	0	9	0	0
T60	0	41	0	0
T66	0	24	0	0
T69	0	16	0	0
T71	0	10	0	0
T97	0	6	0	0
T205	0	8	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T1	230955	27	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	50	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	49	0	0
T35	0	28	0	0
T60	0	106	0	0
T69	0	6	0	0
T71	0	5	0	0
T81	0	4	0	0
T82	0	20	0	0
T204	0	1	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T1	230955	38	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	15	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	9	0	0
T35	0	7	0	0
T60	0	43	0	0
T66	0	51	0	0
T69	0	9	0	0
T97	0	18	0	0
T204	0	4	0	0
T205	0	7	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1786	0	0
T1	230955	20	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	12	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	41	0	0
T35	0	46	0	0
T60	0	32	0	0
T66	0	34	0	0
T69	0	7	0	0
T71	0	10	0	0
T97	0	12	0	0
T204	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T1	230955	22	0	0
T2	48411	0	0	0
T3	11597	0	0	0
T4	42906	16	0	0
T5	63977	0	0	0
T9	115362	0	0	0
T11	91786	0	0	0
T26	22015	0	0	0
T27	25739	0	0	0
T28	29600	0	0	0
T32	0	61	0	0
T34	0	30	0	0
T35	0	2	0	0
T60	0	40	0	0
T69	0	7	0	0
T82	0	13	0	0
T204	0	7	0	0
T206	0	9	0	0