Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1230551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1183965

1

T5

234

T1

600

T6

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2128150	1			T5	72		T1	981		T6	20
values[0x0]	143171	1			T5	86		T1	277		T6	13
values[0x1]	143195	1			T5	104		T1	289		T6	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	990542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1423974

1

T5

253

T1

966

T6

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11030	1			T5	1		T1	6		T25	35
valid_sources[0x01]	7893	1			T5	5		T1	12		T6	2
valid_sources[0x02]	11077	1			T5	1		T1	2		T27	1
valid_sources[0x03]	11246	1			T5	2		T1	11		T25	5
valid_sources[0x04]	7295	1			T1	5		T4	1		T7	10
valid_sources[0x05]	11176	1			T1	7		T27	1		T28	1
valid_sources[0x06]	15501	1			T5	1		T1	5		T6	2
valid_sources[0x07]	8707	1			T1	2		T4	4		T8	3
valid_sources[0x08]	7084	1			T1	7		T25	5		T26	24
valid_sources[0x09]	12629	1			T1	3		T4	1		T7	4
valid_sources[0x0a]	6995	1			T1	7		T28	1		T4	5
valid_sources[0x0b]	11366	1			T5	2		T1	5		T6	1
valid_sources[0x0c]	6960	1			T1	3		T4	3		T7	2
valid_sources[0x0d]	7635	1			T1	6		T28	1		T4	3
valid_sources[0x0e]	6800	1			T1	4		T6	1		T27	4
valid_sources[0x0f]	6587	1			T5	5		T1	5		T27	2
valid_sources[0x10]	8807	1			T1	8		T3	2		T27	3
valid_sources[0x11]	16567	1			T5	4		T1	4		T27	1
valid_sources[0x12]	11005	1			T1	9		T27	4		T4	4
valid_sources[0x13]	7123	1			T5	3		T1	4		T6	1
valid_sources[0x14]	7791	1			T1	8		T27	3		T28	7
valid_sources[0x15]	15652	1			T5	2		T1	8		T25	8
valid_sources[0x16]	6755	1			T1	3		T27	4		T28	1
valid_sources[0x17]	7192	1			T5	2		T1	4		T3	1
valid_sources[0x18]	6430	1			T1	4		T25	1		T27	2
valid_sources[0x19]	6969	1			T1	9		T27	1		T28	1
valid_sources[0x1a]	10677	1			T1	5		T25	1		T27	3
valid_sources[0x1b]	8164	1			T1	8		T6	1		T27	2
valid_sources[0x1c]	6809	1			T5	9		T1	5		T3	2
valid_sources[0x1d]	8897	1			T1	6		T3	13		T28	3
valid_sources[0x1e]	9392	1			T1	6		T3	7		T27	3
valid_sources[0x1f]	6634	1			T1	3		T28	1		T4	2
valid_sources[0x20]	15927	1			T1	5		T3	4		T27	3
valid_sources[0x21]	6587	1			T5	1		T1	6		T27	3
valid_sources[0x22]	6815	1			T5	1		T1	3		T3	23
valid_sources[0x23]	6781	1			T1	12		T27	7		T28	1
valid_sources[0x24]	6834	1			T1	5		T27	1		T4	1
valid_sources[0x25]	8329	1			T5	2		T1	7		T27	2
valid_sources[0x26]	6989	1			T1	9		T27	2		T4	5
valid_sources[0x27]	6760	1			T1	7		T27	2		T28	1
valid_sources[0x28]	11015	1			T1	9		T3	11		T27	2
valid_sources[0x29]	24220	1			T1	4		T27	3		T4	1
valid_sources[0x2a]	6951	1			T5	3		T1	4		T2	39
valid_sources[0x2b]	13910	1			T1	4		T3	2		T27	1
valid_sources[0x2c]	13211	1			T1	5		T25	6		T28	2
valid_sources[0x2d]	7794	1			T1	9		T3	3		T27	1
valid_sources[0x2e]	23855	1			T1	7		T3	7		T4	3
valid_sources[0x2f]	6995	1			T1	2		T27	5		T28	2
valid_sources[0x30]	7392	1			T5	4		T1	6		T27	2
valid_sources[0x31]	6964	1			T5	1		T1	10		T4	2
valid_sources[0x32]	11933	1			T1	7		T27	2		T28	2
valid_sources[0x33]	7711	1			T5	5		T1	9		T3	6
valid_sources[0x34]	7321	1			T1	4		T27	2		T28	2
valid_sources[0x35]	11804	1			T5	4		T1	4		T3	1
valid_sources[0x36]	9295	1			T5	3		T1	4		T6	2
valid_sources[0x37]	11150	1			T1	4		T6	1		T4	4
valid_sources[0x38]	7037	1			T1	1		T2	32		T27	1
valid_sources[0x39]	7294	1			T5	1		T1	5		T27	2
valid_sources[0x3a]	7351	1			T5	2		T1	6		T27	6
valid_sources[0x3b]	7005	1			T5	3		T1	9		T27	1
valid_sources[0x3c]	7832	1			T5	1		T1	9		T3	4
valid_sources[0x3d]	7818	1			T5	4		T1	10		T27	1
valid_sources[0x3e]	20038	1			T5	1		T1	5		T27	2
valid_sources[0x3f]	6720	1			T5	1		T1	6		T27	2
valid_sources[0x40]	10448	1			T1	8		T25	5		T27	4
valid_sources[0x41]	7115	1			T1	6		T27	3		T28	2
valid_sources[0x42]	6755	1			T1	5		T27	1		T4	4
valid_sources[0x43]	15355	1			T1	4		T27	2		T4	1
valid_sources[0x44]	6990	1			T1	9		T6	1		T3	4
valid_sources[0x45]	11041	1			T5	5		T1	2		T3	1
valid_sources[0x46]	6764	1			T1	5		T6	2		T3	10
valid_sources[0x47]	6948	1			T1	3		T27	1		T4	2
valid_sources[0x48]	7105	1			T1	6		T27	2		T4	3
valid_sources[0x49]	8530	1			T5	2		T1	4		T27	2
valid_sources[0x4a]	6692	1			T5	3		T1	7		T2	27
valid_sources[0x4b]	7039	1			T1	10		T25	3		T27	1
valid_sources[0x4c]	27334	1			T1	3		T27	2		T4	1
valid_sources[0x4d]	10416	1			T1	1		T2	8		T4	2
valid_sources[0x4e]	6738	1			T5	2		T1	9		T4	2
valid_sources[0x4f]	7422	1			T5	1		T1	6		T2	6
valid_sources[0x50]	6927	1			T1	3		T3	2		T27	2
valid_sources[0x51]	7049	1			T5	2		T1	5		T25	8
valid_sources[0x52]	6889	1			T5	2		T1	4		T25	1
valid_sources[0x53]	6946	1			T5	1		T1	6		T25	9
valid_sources[0x54]	6448	1			T1	4		T25	1		T27	1
valid_sources[0x55]	13467	1			T1	3		T3	8		T25	1
valid_sources[0x56]	7083	1			T1	10		T27	3		T4	3
valid_sources[0x57]	7860	1			T5	1		T1	10		T3	1
valid_sources[0x58]	6846	1			T5	1		T1	6		T6	1
valid_sources[0x59]	7186	1			T5	4		T1	9		T3	2
valid_sources[0x5a]	15463	1			T5	3		T1	8		T25	7
valid_sources[0x5b]	12767	1			T5	1		T1	11		T28	1
valid_sources[0x5c]	6986	1			T5	3		T1	3		T3	7
valid_sources[0x5d]	6889	1			T5	3		T1	8		T27	1
valid_sources[0x5e]	6552	1			T1	12		T28	1		T4	4
valid_sources[0x5f]	7175	1			T1	7		T27	1		T4	3
valid_sources[0x60]	9533	1			T5	1		T1	7		T27	1
valid_sources[0x61]	12114	1			T1	10		T28	2		T4	5
valid_sources[0x62]	7929	1			T1	8		T27	1		T4	4
valid_sources[0x63]	6827	1			T1	5		T6	1		T3	4
valid_sources[0x64]	11171	1			T1	7		T27	1		T28	2
valid_sources[0x65]	6556	1			T1	3		T3	2		T27	3
valid_sources[0x66]	7224	1			T5	1		T1	6		T4	4
valid_sources[0x67]	16813	1			T1	7		T2	9		T3	3
valid_sources[0x68]	6494	1			T5	5		T1	7		T28	3
valid_sources[0x69]	8303	1			T1	5		T27	1		T4	6
valid_sources[0x6a]	11054	1			T1	2		T6	1		T3	4
valid_sources[0x6b]	8013	1			T5	6		T1	8		T27	1
valid_sources[0x6c]	7919	1			T5	5		T1	4		T3	11
valid_sources[0x6d]	11159	1			T1	6		T27	1		T28	6
valid_sources[0x6e]	6496	1			T1	4		T3	6		T28	1
valid_sources[0x6f]	9103	1			T1	8		T27	3		T4	5
valid_sources[0x70]	7005	1			T1	3		T27	3		T28	2
valid_sources[0x71]	10255	1			T1	10		T25	11		T27	1
valid_sources[0x72]	6912	1			T1	8		T4	2		T7	3
valid_sources[0x73]	6811	1			T1	4		T3	2		T27	1
valid_sources[0x74]	6792	1			T5	1		T1	6		T27	1
valid_sources[0x75]	10592	1			T5	1		T1	6		T6	1
valid_sources[0x76]	9741	1			T1	3		T3	1		T27	2
valid_sources[0x77]	6845	1			T5	5		T1	4		T28	2
valid_sources[0x78]	19964	1			T1	9		T27	3		T28	2
valid_sources[0x79]	11289	1			T1	9		T25	5		T27	3
valid_sources[0x7a]	7806	1			T5	2		T1	7		T25	1
valid_sources[0x7b]	8541	1			T5	1		T1	5		T3	9
valid_sources[0x7c]	6457	1			T1	8		T3	1		T4	2
valid_sources[0x7d]	6725	1			T5	1		T1	8		T3	5
valid_sources[0x7e]	6521	1			T1	5		T27	3		T28	2
valid_sources[0x7f]	12146	1			T1	7		T25	16		T4	3
valid_sources[0x80]	7331	1			T5	1		T1	8		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1062152

1

T5

65

T1

138

T6

12

values[0x0]

all_enables

biggest_size

71400

1

T5

83

T1

236

T6

5

values[0x1]

all_enables

biggest_size

50413

1

T5

86

T1

226

T2

35