Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28375	1			T1	2		T9	12		T11	5
auto[PWRUP]	112	1			T38	1		T39	2		T40	2
auto[ONEST_0]	78	1			T38	1		T39	1		T175	1
auto[ONEST_021]	17	1			T44	1		T176	1		T177	1
auto[ONEST_1]	73	1			T38	1		T40	1		T175	2
auto[ONEST_DONE]	7	1			T178	1		T179	1		T180	1
auto[LP_0]	98	1			T38	2		T39	1		T40	1
auto[LP_021]	17	1			T175	2		T181	1		T176	1
auto[LP_1]	137	1			T38	1		T39	1		T175	2
auto[LP_EVAL]	94	1			T38	1		T40	4		T181	2
auto[LP_SLP]	497	1			T38	5		T39	6		T40	11
auto[LP_PWRUP]	31	1			T39	1		T44	2		T182	2
auto[NP_0]	157	1			T38	2		T39	1		T40	2
auto[NP_021]	28	1			T38	2		T39	1		T40	1
auto[NP_1]	139	1			T38	1		T39	3		T40	4
auto[NP_EVAL]	37	1			T39	3		T181	1		T98	2
auto[NP_DONE]	1	1			T183	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T184

1

T141

1

T143

1

min

27828

1

T1

2

T9

12

T11

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27835	1			T1	2		T9	12		T11	5
pow[0x1]	12	1			T185	1		T186	1		T187	1
pow[0x2]	12	1			T143	1		T188	1		T189	1
pow[0x3]	32	1			T40	1		T181	1		T176	1
pow[0x4]	69	1			T181	1		T44	2		T176	2
pow[0x5]	135	1			T39	3		T40	4		T175	3
pow[0x6]	246	1			T38	2		T39	1		T40	1
pow[0x7]	508	1			T38	5		T39	5		T40	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

208

1

T39

1

T40

2

T175

3

min

27344

1

T1

2

T9

12

T11

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27344	1			T1	2		T9	12		T11	5
pow[0x3]	2	1			T189	1		T190	1		-	-
pow[0x5]	1	1			T191	1		-	-		-	-
pow[0x7]	3	1			T178	1		T55	1		T192	1
pow[0x8]	4	1			T193	1		T194	1		T195	1
pow[0x9]	7	1			T196	1		T197	2		T190	1
pow[0xa]	15	1			T177	1		T141	1		T143	1
pow[0xb]	31	1			T39	1		T176	1		T178	1
pow[0xc]	60	1			T39	4		T175	1		T181	1
pow[0xd]	151	1			T38	2		T39	1		T40	3
pow[0xe]	322	1			T38	2		T39	7		T40	4
pow[0xf]	578	1			T38	6		T39	7		T40	6