Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2184	1			T1	20		T2	1		T4	10
auto[PWRUP]	122	1			T239	1		T38	2		T39	1
auto[ONEST_0]	86	1			T19	2		T38	1		T39	4
auto[ONEST_021]	15	1			T39	1		T44	1		T332	1
auto[ONEST_1]	86	1			T19	1		T38	1		T40	1
auto[ONEST_DONE]	4	1			T333	1		T334	1		T335	1
auto[LP_0]	130	1			T38	1		T39	2		T40	3
auto[LP_021]	32	1			T38	2		T175	1		T181	3
auto[LP_1]	132	1			T38	1		T39	1		T40	2
auto[LP_EVAL]	67	1			T38	1		T175	1		T44	1
auto[LP_SLP]	540	1			T19	1		T239	1		T38	6
auto[LP_PWRUP]	32	1			T38	1		T39	1		T193	1
auto[NP_0]	237	1			T12	1		T38	3		T43	2
auto[NP_021]	49	1			T181	1		T98	2		T214	2
auto[NP_1]	223	1			T12	2		T239	1		T38	2
auto[NP_EVAL]	31	1			T12	1		T239	1		T87	1
auto[NP_DONE]	1	1			T336	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T181

1

T98

1

T195

1

min

1846

1

T1

20

T2

1

T4

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1854	1			T1	20		T2	1		T4	10
pow[0x1]	13	1			T178	1		T337	1		T338	1
pow[0x2]	15	1			T39	1		T332	1		T58	1
pow[0x3]	39	1			T175	1		T181	1		T214	1
pow[0x4]	67	1			T38	1		T181	2		T44	1
pow[0x5]	143	1			T38	3		T39	3		T175	2
pow[0x6]	267	1			T38	5		T39	2		T40	4
pow[0x7]	552	1			T38	10		T39	8		T40	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

201

1

T38

4

T39

2

T40

2

min

1276

1

T1

20

T2

1

T4

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1280	1			T1	20		T2	1		T4	10
pow[0x1]	10	1			T280	4		T339	1		T340	1
pow[0x2]	10	1			T98	1		T208	1		T240	2
pow[0x3]	48	1			T12	3		T239	1		T98	1
pow[0x4]	61	1			T12	1		T43	3		T87	2
pow[0x7]	1	1			T181	1		-	-		-	-
pow[0x8]	2	1			T341	1		T342	1		-	-
pow[0x9]	6	1			T38	1		T176	1		T195	1
pow[0xa]	14	1			T178	1		T143	1		T343	1
pow[0xb]	35	1			T38	1		T40	1		T175	1
pow[0xc]	76	1			T38	4		T175	1		T181	2
pow[0xd]	144	1			T38	2		T39	4		T175	2
pow[0xe]	305	1			T38	3		T39	1		T40	5
pow[0xf]	594	1			T38	5		T39	6		T40	8