Unified Coverage Report :: Module :: adc_ctrl_reg_top

Module : adc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.77	98.90	95.13	100.00		98.47	96.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_chn0_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_ext_0	55.19	55.56	50.00			60.00
u_adc_chn_val_0_adc_chn_value_intr_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_ext_0	55.19	55.56	50.00			60.00
u_adc_chn_val_0_cdc	75.53	95.31	57.35			89.47	60.00
u_adc_chn_val_1_adc_chn_value_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_ext_1	55.19	55.56	50.00			60.00
u_adc_chn_val_1_adc_chn_value_intr_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_ext_1	55.19	55.56	50.00			60.00
u_adc_chn_val_1_cdc	75.53	95.31	57.35			89.47	60.00
u_adc_en_ctl_adc_enable	100.00	100.00	100.00			100.00
u_adc_en_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_en_ctl_oneshot_mode	100.00	100.00	100.00			100.00
u_adc_fsm_rst	100.00	100.00	100.00			100.00
u_adc_fsm_rst_cdc	99.22	100.00	96.88			100.00	100.00
u_adc_intr_ctl	100.00	100.00	100.00			100.00
u_adc_intr_status_filter_match	100.00	100.00	100.00			100.00
u_adc_intr_status_oneshot	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_lp_mode	100.00	100.00	100.00			100.00
u_adc_pd_ctl_pwrup_time	100.00	100.00	100.00			100.00
u_adc_pd_ctl_wakeup_time	100.00	100.00	100.00			100.00
u_adc_sample_ctl	100.00	100.00	100.00			100.00
u_adc_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl	100.00	100.00	100.00			100.00
u_adc_wakeup_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_filter_status	100.00	100.00	100.00			100.00
u_filter_status_cdc	96.76	100.00	88.73			98.31	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		324	324	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	231	3	3	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	272	4	4	100.00
CONT_ASSIGN	302	1	1	100.00
ALWAYS	312	2	2	100.00
CONT_ASSIGN	340	1	1	100.00
ALWAYS	350	2	2	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	388	2	2	100.00
CONT_ASSIGN	416	1	1	100.00
ALWAYS	429	5	5	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	473	5	5	100.00
CONT_ASSIGN	504	1	1	100.00
ALWAYS	517	5	5	100.00
CONT_ASSIGN	548	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	592	1	1	100.00
ALWAYS	605	5	5	100.00
CONT_ASSIGN	636	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	680	1	1	100.00
ALWAYS	693	5	5	100.00
CONT_ASSIGN	724	1	1	100.00
ALWAYS	737	5	5	100.00
CONT_ASSIGN	768	1	1	100.00
ALWAYS	781	5	5	100.00
CONT_ASSIGN	812	1	1	100.00
ALWAYS	825	5	5	100.00
CONT_ASSIGN	856	1	1	100.00
ALWAYS	869	5	5	100.00
CONT_ASSIGN	900	1	1	100.00
ALWAYS	913	5	5	100.00
CONT_ASSIGN	944	1	1	100.00
ALWAYS	957	5	5	100.00
CONT_ASSIGN	988	1	1	100.00
ALWAYS	1001	5	5	100.00
CONT_ASSIGN	1032	1	1	100.00
ALWAYS	1045	5	5	100.00
CONT_ASSIGN	1076	1	1	100.00
ALWAYS	1089	5	5	100.00
CONT_ASSIGN	1120	1	1	100.00
ALWAYS	1136	10	10	100.00
ALWAYS	1186	10	10	100.00
ALWAYS	1230	2	2	100.00
CONT_ASSIGN	1258	1	1	100.00
ALWAYS	1271	4	4	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1378	1	1	100.00
CONT_ASSIGN	1384	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	3403	1	1	100.00
CONT_ASSIGN	3516	1	1	100.00
CONT_ASSIGN	3656	1	1	100.00
ALWAYS	3771	32	32	100.00
CONT_ASSIGN	3805	1	1	100.00
ALWAYS	3809	1	1	100.00
CONT_ASSIGN	3844	1	1	100.00
CONT_ASSIGN	3846	1	1	100.00
CONT_ASSIGN	3847	1	1	100.00
CONT_ASSIGN	3849	1	1	100.00
CONT_ASSIGN	3850	1	1	100.00
CONT_ASSIGN	3852	1	1	100.00
CONT_ASSIGN	3853	1	1	100.00
CONT_ASSIGN	3855	1	1	100.00
CONT_ASSIGN	3856	1	1	100.00
CONT_ASSIGN	3859	1	1	100.00
CONT_ASSIGN	3863	1	1	100.00
CONT_ASSIGN	3865	1	1	100.00
CONT_ASSIGN	3867	1	1	100.00
CONT_ASSIGN	3869	1	1	100.00
CONT_ASSIGN	3874	1	1	100.00
CONT_ASSIGN	3879	1	1	100.00
CONT_ASSIGN	3884	1	1	100.00
CONT_ASSIGN	3889	1	1	100.00
CONT_ASSIGN	3894	1	1	100.00
CONT_ASSIGN	3899	1	1	100.00
CONT_ASSIGN	3904	1	1	100.00
CONT_ASSIGN	3909	1	1	100.00
CONT_ASSIGN	3914	1	1	100.00
CONT_ASSIGN	3919	1	1	100.00
CONT_ASSIGN	3924	1	1	100.00
CONT_ASSIGN	3929	1	1	100.00
CONT_ASSIGN	3934	1	1	100.00
CONT_ASSIGN	3939	1	1	100.00
CONT_ASSIGN	3944	1	1	100.00
CONT_ASSIGN	3949	1	1	100.00
CONT_ASSIGN	3951	1	1	100.00
CONT_ASSIGN	3953	1	1	100.00
CONT_ASSIGN	3955	1	1	100.00
CONT_ASSIGN	3956	1	1	100.00
CONT_ASSIGN	3958	1	1	100.00
CONT_ASSIGN	3960	1	1	100.00
ALWAYS	3964	32	32	100.00
ALWAYS	4000	34	34	100.00
CONT_ASSIGN	4114	1	1	100.00
ALWAYS	4116	27	27	100.00
CONT_ASSIGN	4206	1	1	100.00
CONT_ASSIGN	4207	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
231	1	1
232	1	1
233	1	1
260	1	1
272	1	1
273	1	1
274	1	1
275	1	1
302	1	1
312	1	1
313	1	1
340	1	1
350	1	1
351	1	1
378	1	1
388	1	1
389	1	1
416	1	1
429	1	1
430	1	1
431	1	1
432	1	1
433	1	1
460	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
504	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
548	1	1
561	1	1
562	1	1
563	1	1
564	1	1
565	1	1
592	1	1
605	1	1
606	1	1
607	1	1
608	1	1
609	1	1
636	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
680	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
724	1	1
737	1	1
738	1	1
739	1	1
740	1	1
741	1	1
768	1	1
781	1	1
782	1	1
783	1	1
784	1	1
785	1	1
812	1	1
825	1	1
826	1	1
827	1	1
828	1	1
829	1	1
856	1	1
869	1	1
870	1	1
871	1	1
872	1	1
873	1	1
900	1	1
913	1	1
914	1	1
915	1	1
916	1	1
917	1	1
944	1	1
957	1	1
958	1	1
959	1	1
960	1	1
961	1	1
988	1	1
1001	1	1
1002	1	1
1003	1	1
1004	1	1
1005	1	1
1032	1	1
1045	1	1
1046	1	1
1047	1	1
1048	1	1
1049	1	1
1076	1	1
1089	1	1
1090	1	1
1091	1	1
1092	1	1
1093	1	1
1120	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1230	1	1
1231	1	1
1258	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1301	1	1
1364	1	1
1378	1	1
1384	1	1
1398	1	1
3403	1	1
3516	1	1
3656	1	1
3771	1	1
3772	1	1
3773	1	1
3774	1	1
3775	1	1
3776	1	1
3777	1	1
3778	1	1
3779	1	1
3780	1	1
3781	1	1
3782	1	1
3783	1	1
3784	1	1
3785	1	1
3786	1	1
3787	1	1
3788	1	1
3789	1	1
3790	1	1
3791	1	1
3792	1	1
3793	1	1
3794	1	1
3795	1	1
3796	1	1
3797	1	1
3798	1	1
3799	1	1
3800	1	1
3801	1	1
3802	1	1
3805	1	1
3809	1	1
3844	1	1
3846	1	1
3847	1	1
3849	1	1
3850	1	1
3852	1	1
3853	1	1
3855	1	1
3856	1	1
3859	1	1
3863	1	1
3865	1	1
3867	1	1
3869	1	1
3874	1	1
3879	1	1
3884	1	1
3889	1	1
3894	1	1
3899	1	1
3904	1	1
3909	1	1
3914	1	1
3919	1	1
3924	1	1
3929	1	1
3934	1	1
3939	1	1
3944	1	1
3949	1	1
3951	1	1
3953	1	1
3955	1	1
3956	1	1
3958	1	1
3960	1	1
3964	1	1
3965	1	1
3966	1	1
3967	1	1
3968	1	1
3969	1	1
3970	1	1
3971	1	1
3972	1	1
3973	1	1
3974	1	1
3975	1	1
3976	1	1
3977	1	1
3978	1	1
3979	1	1
3980	1	1
3981	1	1
3982	1	1
3983	1	1
3984	1	1
3985	1	1
3986	1	1
3987	1	1
3988	1	1
3989	1	1
3990	1	1
3991	1	1
3992	1	1
3993	1	1
3994	1	1
3995	1	1
4000	1	1
4001	1	1
4003	1	1
4007	1	1
4011	1	1
4015	1	1
4019	1	1
4022	1	1
4025	1	1
4028	1	1
4031	1	1
4034	1	1
4037	1	1
4040	1	1
4043	1	1
4046	1	1
4049	1	1
4052	1	1
4055	1	1
4058	1	1
4061	1	1
4064	1	1
4067	1	1
4070	1	1
4073	1	1
4076	1	1
4079	1	1
4082	1	1
4085	1	1
4088	1	1
4091	1	1
4094	1	1
4098	1	1
4099	1	1
4114	1	1
4116	1	1
4117	1	1
4119	1	1
4122	1	1
4125	1	1
4128	1	1
4131	1	1
4134	1	1
4137	1	1
4140	1	1
4143	1	1
4146	1	1
4149	1	1
4152	1	1
4155	1	1
4158	1	1
4161	1	1
4164	1	1
4167	1	1
4170	1	1
4173	1	1
4176	1	1
4179	1	1
4182	1	1
4185	1	1
4188	1	1
4191	1	1
4206	1	1
4207	1	1

---

Cond Coverage for Module : adc_ctrl_reg_top

	Total	Covered	Percent
Conditions	329	329	100.00
Logical	329	329	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T25,T27
1	1	Covered	T5,T1,T6

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T48,T49,T50
1	0	Covered	T1,T4,T10

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T1,T6
0	0	1	Covered	T48,T49,T50
0	1	0	Covered	T1,T4,T10
1	0	0	Covered	T1,T4,T10

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T1,T6
0	0	1	Covered	T1,T4,T10
0	1	0	Covered	T5,T25,T27
1	0	0	Covered	T5,T25,T27

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T25

 LINE       3772
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3773
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3774
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3775
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3776
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_EN_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3777
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_PD_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3778
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3779
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_SAMPLE_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3780
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_RST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3781
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3782
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3783
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3784
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3785
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3786
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3787
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3788
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3789
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3790
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3791
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3792
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3793
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3794
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3795
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3796
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3797
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_0_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3798
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_1_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3799
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_WAKEUP_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3800
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_FILTER_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3801
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_CTL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3802
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_STATUS_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       3805
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       3805
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6

 LINE       3809
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T25,T27

 LINE       3809
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T5,T1,T6
31 (addr_hit[30] & ((|(4'...	Covered	T5,T1,T25
30 (addr_hit[29] & ((|(4'...	Covered	T5,T1,T2
29 (addr_hit[28] & ((|(4'...	Covered	T5,T1,T25
28 (addr_hit[27] & ((|(4'...	Covered	T5,T1,T2
27 (addr_hit[26] & ((|(4'...	Covered	T5,T1,T2
26 (addr_hit[25] & ((|(4'...	Covered	T5,T1,T2
25 (addr_hit[24] & ((|(4'...	Covered	T5,T1,T2
24 (addr_hit[23] & ((|(4'...	Covered	T5,T1,T2
23 (addr_hit[22] & ((|(4'...	Covered	T5,T1,T2
22 (addr_hit[21] & ((|(4'...	Covered	T5,T1,T25
21 (addr_hit[20] & ((|(4'...	Covered	T5,T1,T2
20 (addr_hit[19] & ((|(4'...	Covered	T5,T1,T2
19 (addr_hit[18] & ((|(4'...	Covered	T5,T1,T25
18 (addr_hit[17] & ((|(4'...	Covered	T5,T1,T2
17 (addr_hit[16] & ((|(4'...	Covered	T5,T1,T25
16 (addr_hit[15] & ((|(4'...	Covered	T5,T1,T2
15 (addr_hit[14] & ((|(4'...	Covered	T5,T1,T2
14 (addr_hit[13] & ((|(4'...	Covered	T5,T1,T25
13 (addr_hit[12] & ((|(4'...	Covered	T5,T1,T2
12 (addr_hit[11] & ((|(4'...	Covered	T5,T1,T2
11 (addr_hit[10] & ((|(4'...	Covered	T5,T1,T2
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T1,T2
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T1,T2
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T1,T25
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T1,T25
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T1,T2
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T1,T25
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T1,T2
3 (addr_hit[2] & ((|(4'b...	Covered	T5,T1,T6
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T1,T6
1 (addr_hit[0] & ((|(4'b...	Covered	T5,T1,T6

 LINE       3809
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       3809
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       3809
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       3809
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3809
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       3809
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T25

 LINE       3844
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T6
1	1	0	Covered	T64,T67,T68
1	1	1	Covered	T6,T26,T31

 LINE       3847
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T6
1	1	0	Covered	T25,T27,T63
1	1	1	Covered	T1,T6,T2

 LINE       3850
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T6
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T6,T26,T31

 LINE       3853
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T4
1	1	1	Covered	T1,T2,T3

 LINE       3856
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3859
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3863
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T6
1	1	0	Covered	T1,T25,T27
1	1	1	Covered	T5,T1,T6

 LINE       3865
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T6
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T5,T1,T6

 LINE       3867
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T4

 LINE       3869
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3874
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T27,T63,T68
1	1	1	Covered	T1,T2,T3

 LINE       3879
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3884
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3889
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3894
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T63
1	1	1	Covered	T1,T2,T3

 LINE       3899
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3904
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3909
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3914
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3919
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3924
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3929
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T63
1	1	1	Covered	T1,T2,T4

 LINE       3934
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3939
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       3944
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3949
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T25,T27
1	1	1	Covered	T1,T2,T3

 LINE       3951
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T5,T27,T64
1	1	1	Covered	T1,T2,T3

 LINE       3953
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T1,T25,T28
1	1	1	Covered	T1,T2,T3

 LINE       3956
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T6
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T25,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       4114
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T1,T6

---

Branch Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		63	63	100.00
TERNARY	3805	2	2	100.00
IF	73	3	3	100.00
CASE	4001	32	32	100.00
CASE	4117	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3805	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T6
0	1	Covered	T1,T4,T10
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	4001	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T1,T6
addr_hit[1]	Covered	T5,T1,T6
addr_hit[2]	Covered	T5,T1,T6
addr_hit[3]	Covered	T5,T1,T6
addr_hit[4]	Covered	T5,T1,T6
addr_hit[5]	Covered	T5,T1,T6
addr_hit[6]	Covered	T5,T1,T6
addr_hit[7]	Covered	T5,T1,T6
addr_hit[8]	Covered	T5,T1,T6
addr_hit[9]	Covered	T5,T1,T6
addr_hit[10]	Covered	T5,T1,T6
addr_hit[11]	Covered	T5,T1,T6
addr_hit[12]	Covered	T5,T1,T6
addr_hit[13]	Covered	T5,T1,T6
addr_hit[14]	Covered	T5,T1,T6
addr_hit[15]	Covered	T5,T1,T6
addr_hit[16]	Covered	T5,T1,T6
addr_hit[17]	Covered	T5,T1,T6
addr_hit[18]	Covered	T5,T1,T6
addr_hit[19]	Covered	T5,T1,T6
addr_hit[20]	Covered	T5,T1,T6
addr_hit[21]	Covered	T5,T1,T6
addr_hit[22]	Covered	T5,T1,T6
addr_hit[23]	Covered	T5,T1,T6
addr_hit[24]	Covered	T5,T1,T6
addr_hit[25]	Covered	T5,T1,T6
addr_hit[26]	Covered	T5,T1,T6
addr_hit[27]	Covered	T5,T1,T6
addr_hit[28]	Covered	T5,T1,T6
addr_hit[29]	Covered	T5,T1,T6
addr_hit[30]	Covered	T5,T1,T6
default	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	4117	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T5,T1,T6
addr_hit[5]	Covered	T5,T1,T6
addr_hit[6]	Covered	T5,T1,T6
addr_hit[7]	Covered	T5,T1,T6
addr_hit[8]	Covered	T5,T1,T6
addr_hit[9]	Covered	T5,T1,T6
addr_hit[10]	Covered	T5,T1,T6
addr_hit[11]	Covered	T5,T1,T6
addr_hit[12]	Covered	T5,T1,T6
addr_hit[13]	Covered	T5,T1,T6
addr_hit[14]	Covered	T5,T1,T6
addr_hit[15]	Covered	T5,T1,T6
addr_hit[16]	Covered	T5,T1,T6
addr_hit[17]	Covered	T5,T1,T6
addr_hit[18]	Covered	T5,T1,T6
addr_hit[19]	Covered	T5,T1,T6
addr_hit[20]	Covered	T5,T1,T6
addr_hit[21]	Covered	T5,T1,T6
addr_hit[22]	Covered	T5,T1,T6
addr_hit[23]	Covered	T5,T1,T6
addr_hit[24]	Covered	T5,T1,T6
addr_hit[25]	Covered	T5,T1,T6
addr_hit[26]	Covered	T5,T1,T6
addr_hit[27]	Covered	T5,T1,T6
addr_hit[28]	Covered	T5,T1,T6
default	Covered	T5,T1,T6

---

Assert Coverage for Module : adc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2407638	0	0
reAfterRv	2147483647	2407636	0	0
rePulse	2147483647	2126417	0	0
wePulse	2147483647	281219	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407638	0	0
T1	793301	1543	0	0
T2	4351	126	0	0
T3	47255	283	0	0
T4	448599	778	0	0
T5	13643	30	0	0
T6	2690	42	0	0
T25	27182	75	0	0
T26	7978	24	0	0
T27	45302	68	0	0
T28	39928	27	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407636	0	0
T1	793301	1543	0	0
T2	4351	126	0	0
T3	47255	283	0	0
T4	448599	778	0	0
T5	13643	30	0	0
T6	2690	42	0	0
T25	27182	75	0	0
T26	7978	24	0	0
T27	45302	68	0	0
T28	39928	27	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2126417	0	0
T1	793301	980	0	0
T2	4351	95	0	0
T3	47255	143	0	0
T4	448599	507	0	0
T5	13643	8	0	0
T6	2690	20	0	0
T25	27182	4	0	0
T26	7978	11	0	0
T27	45302	4	0	0
T28	39928	6	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	281219	0	0
T1	793301	563	0	0
T2	4351	31	0	0
T3	47255	140	0	0
T4	448599	271	0	0
T5	13643	22	0	0
T6	2690	22	0	0
T25	27182	71	0	0
T26	7978	13	0	0
T27	45302	64	0	0
T28	39928	21	0	0