Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T19,T20

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T21
1	0	Covered	T12,T13,T16
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T16
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T16
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T16
1	1	0	Covered	T12,T13,T15
1	1	1	Covered	T12,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T16
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T15
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T15
1	1	0	Covered	T12,T13,T15
1	1	1	Covered	T12,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T15
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T15
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T19,T20
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32915197	32608100	0	0
gen_filter_match[0].MatchCheck00_A	32915197	8870309	0	0
gen_filter_match[0].MatchCheck01_A	32915197	2686615	0	0
gen_filter_match[0].MatchCheck10_A	32915197	2479691	0	0
gen_filter_match[0].MatchCheck11_A	32915197	18571485	0	0
gen_filter_match[1].MatchCheck00_A	32915197	10981450	0	0
gen_filter_match[1].MatchCheck01_A	32915197	1176449	0	0
gen_filter_match[1].MatchCheck10_A	32915197	1201544	0	0
gen_filter_match[1].MatchCheck11_A	32915197	19248657	0	0
gen_filter_match[2].MatchCheck00_A	32915197	11666704	0	0
gen_filter_match[2].MatchCheck01_A	32915197	621754	0	0
gen_filter_match[2].MatchCheck10_A	32915197	930989	0	0
gen_filter_match[2].MatchCheck11_A	32915197	19388653	0	0
gen_filter_match[3].MatchCheck00_A	32915197	12414330	0	0
gen_filter_match[3].MatchCheck01_A	32915197	533219	0	0
gen_filter_match[3].MatchCheck10_A	32915197	190220	0	0
gen_filter_match[3].MatchCheck11_A	32915197	19470331	0	0
gen_filter_match[4].MatchCheck00_A	32915197	12663408	0	0
gen_filter_match[4].MatchCheck01_A	32915197	14	0	0
gen_filter_match[4].MatchCheck10_A	32915197	33399	0	0
gen_filter_match[4].MatchCheck11_A	32915197	19911279	0	0
gen_filter_match[5].MatchCheck00_A	32915197	12956827	0	0
gen_filter_match[5].MatchCheck01_A	32915197	16	0	0
gen_filter_match[5].MatchCheck10_A	32915197	32651	0	0
gen_filter_match[5].MatchCheck11_A	32915197	19618606	0	0
gen_filter_match[6].MatchCheck00_A	32915197	12409952	0	0
gen_filter_match[6].MatchCheck01_A	32915197	65923	0	0
gen_filter_match[6].MatchCheck10_A	32915197	64519	0	0
gen_filter_match[6].MatchCheck11_A	32915197	20067706	0	0
gen_filter_match[7].MatchCheck00_A	32915197	11826178	0	0
gen_filter_match[7].MatchCheck01_A	32915197	130022	0	0
gen_filter_match[7].MatchCheck10_A	32915197	96922	0	0
gen_filter_match[7].MatchCheck11_A	32915197	20554978	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	32608100	0	0
T12	87604	87041	0	0
T13	99090	98997	0	0
T14	66245	66148	0	0
T15	32463	32388	0	0
T16	97868	97817	0	0
T17	99090	98996	0	0
T18	8304	8232	0	0
T19	2928	2432	0	0
T20	1144	1068	0	0
T21	33444	33360	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	8870309	0	0
T12	87604	60656	0	0
T13	99090	3	0	0
T14	66245	33319	0	0
T15	32463	32388	0	0
T16	97868	4	0	0
T17	99090	65907	0	0
T18	8304	8232	0	0
T19	2928	2432	0	0
T20	1144	1068	0	0
T21	33444	4	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	2686615	0	0
T14	66245	32829	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	33356	0	0
T22	66543	0	0	0
T23	32814	0	0	0
T92	0	33211	0	0
T93	0	33802	0	0
T94	0	32920	0	0
T95	0	33016	0	0
T96	0	32637	0	0
T97	0	32739	0	0
T98	0	45027	0	0
T99	0	33307	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	2479691	0	0
T13	99090	33907	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T23	0	1	0	0
T43	0	9271	0	0
T62	0	2	0	0
T94	0	31947	0	0
T98	0	2753	0	0
T100	0	32169	0	0
T101	0	33005	0	0
T102	0	32012	0	0
T103	0	34558	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	18571485	0	0
T12	87604	26385	0	0
T13	99090	65087	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	97813	0	0
T17	99090	33089	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	0	66440	0	0
T23	0	32759	0	0
T62	0	32525	0	0
T104	0	98319	0	0
T105	0	98239	0	0
T106	0	34947	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	10981450	0	0
T12	87604	1081	0	0
T13	99090	33910	0	0
T14	66245	66148	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	33106	0	0
T18	8304	8232	0	0
T19	2928	2327	0	0
T20	1144	1068	0	0
T21	33444	33360	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	1176449	0	0
T15	32463	32384	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	105	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T23	32814	0	0	0
T24	66185	0	0	0
T86	0	32506	0	0
T102	0	33489	0	0
T104	0	32964	0	0
T105	0	32145	0	0
T107	0	33222	0	0
T108	0	32483	0	0
T109	0	32707	0	0
T110	0	32802	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	1201544	0	0
T12	87604	26385	0	0
T13	99090	0	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	0	33697	0	0
T24	0	32884	0	0
T62	0	3	0	0
T87	0	13121	0	0
T92	0	1	0	0
T96	0	65509	0	0
T111	0	1	0	0
T112	0	32980	0	0
T113	0	32784	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	19248657	0	0
T12	87604	59575	0	0
T13	99090	65087	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	97813	0	0
T17	99090	65890	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	0	32743	0	0
T24	0	31868	0	0
T62	0	32524	0	0
T92	0	33211	0	0
T104	0	65355	0	0
T106	0	67844	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	11666704	0	0
T12	87604	27466	0	0
T13	99090	65851	0	0
T14	66245	33319	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	98996	0	0
T18	8304	8232	0	0
T19	2928	2432	0	0
T20	1144	1068	0	0
T21	33444	3	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	621754	0	0
T12	87604	59575	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T57	0	33226	0	0
T93	0	1	0	0
T114	0	35068	0	0
T115	0	34215	0	0
T116	0	33416	0	0
T117	0	33351	0	0
T118	0	33658	0	0
T119	0	31792	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	930989	0	0
T21	33444	2	0	0
T22	66543	0	0	0
T23	32814	1	0	0
T24	66185	31868	0	0
T41	7881	0	0	0
T42	7611	0	0	0
T44	0	54317	0	0
T62	32605	0	0	0
T88	1111	0	0	0
T89	904	0	0	0
T92	0	1	0	0
T96	0	1	0	0
T101	0	33372	0	0
T103	0	31787	0	0
T104	98374	0	0	0
T111	0	1	0	0
T113	0	66145	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	19388653	0	0
T13	99090	33145	0	0
T14	66245	32829	0	0
T15	32463	32384	0	0
T16	97868	97813	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	33355	0	0
T22	66543	32743	0	0
T23	0	32759	0	0
T24	0	32884	0	0
T92	0	33211	0	0
T104	0	65587	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	12414330	0	0
T12	87604	27466	0	0
T13	99090	3	0	0
T14	66245	66148	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	3	0	0
T18	8304	8232	0	0
T19	2928	2327	0	0
T20	1144	1068	0	0
T21	33444	33360	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	533219	0	0
T17	99090	32801	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T23	32814	0	0	0
T24	66185	0	0	0
T35	0	32352	0	0
T41	7881	0	0	0
T88	1111	0	0	0
T93	0	1	0	0
T103	0	32788	0	0
T110	0	32628	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	4062	0	0
T122	0	1	0	0
T123	0	2416	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	190220	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T23	0	2	0	0
T62	0	2	0	0
T93	0	1	0	0
T96	0	1	0	0
T111	0	1	0	0
T120	0	1	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	19470331	0	0
T12	87604	59575	0	0
T13	99090	98993	0	0
T14	66245	0	0	0
T15	32463	32384	0	0
T16	97868	97813	0	0
T17	99090	66192	0	0
T18	8304	0	0	0
T19	2928	105	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	0	33697	0	0
T23	0	32758	0	0
T24	0	31868	0	0
T62	0	32524	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	12663408	0	0
T12	87604	27466	0	0
T13	99090	33909	0	0
T14	66245	32832	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	33092	0	0
T18	8304	8232	0	0
T19	2928	2327	0	0
T20	1144	1068	0	0
T21	33444	4	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	14	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T122	0	2	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	33399	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	1	0	0
T22	66543	0	0	0
T23	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T96	0	1	0	0
T111	0	1	0	0
T124	0	2	0	0
T133	0	1	0	0
T134	0	33325	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	19911279	0	0
T12	87604	59575	0	0
T13	99090	65086	0	0
T14	66245	33316	0	0
T15	32463	32384	0	0
T16	97868	97813	0	0
T17	99090	65904	0	0
T18	8304	0	0	0
T19	2928	105	0	0
T20	1144	0	0	0
T21	33444	33355	0	0
T22	0	32743	0	0
T23	0	32758	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	12956827	0	0
T12	87604	27466	0	0
T13	99090	65090	0	0
T14	66245	33319	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	33092	0	0
T18	8304	8232	0	0
T19	2928	2327	0	0
T20	1144	1068	0	0
T21	33444	4	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	16	0	0
T120	66827	1	0	0
T122	0	1	0	0
T128	66005	1	0	0
T129	0	1	0	0
T131	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	8682	0	0	0
T141	24430	0	0	0
T142	33857	0	0	0
T143	57768	0	0	0
T144	33422	0	0	0
T145	1195	0	0	0
T146	100644	0	0	0
T147	1185	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	32651	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	1	0	0
T22	66543	0	0	0
T93	0	1	0	0
T111	0	1	0	0
T120	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T133	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	19618606	0	0
T12	87604	59575	0	0
T13	99090	33906	0	0
T14	66245	32829	0	0
T15	32463	32384	0	0
T16	97868	97813	0	0
T17	99090	65904	0	0
T18	8304	0	0	0
T19	2928	105	0	0
T20	1144	0	0	0
T21	33444	33355	0	0
T22	0	33697	0	0
T24	0	64752	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	12409952	0	0
T12	87604	1081	0	0
T13	99090	33148	0	0
T14	66245	3	0	0
T15	32463	32388	0	0
T16	97868	4	0	0
T17	99090	66195	0	0
T18	8304	8232	0	0
T19	2928	2432	0	0
T20	1144	1068	0	0
T21	33444	33360	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	65923	0	0
T96	98210	1	0	0
T124	67341	0	0	0
T127	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T139	0	1	0	0
T149	96809	33072	0	0
T150	0	32842	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	66896	0	0	0
T154	99585	0	0	0
T155	32883	0	0	0
T156	33610	0	0	0
T157	66498	0	0	0
T158	6827	0	0	0
T159	65437	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	64519	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T23	0	1	0	0
T62	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T96	0	1	0	0
T98	0	2	0	0
T111	0	1	0	0
T124	0	1	0	0
T133	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	20067706	0	0
T12	87604	85960	0	0
T13	99090	65848	0	0
T14	66245	66145	0	0
T15	32463	0	0	0
T16	97868	97813	0	0
T17	99090	32801	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	0	32743	0	0
T23	0	32758	0	0
T62	0	32523	0	0
T92	0	33210	0	0
T104	0	65587	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	11826178	0	0
T12	87604	60656	0	0
T13	99090	31944	0	0
T14	66245	33319	0	0
T15	32463	4	0	0
T16	97868	4	0	0
T17	99090	65893	0	0
T18	8304	8232	0	0
T19	2928	2327	0	0
T20	1144	1068	0	0
T21	33444	4	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	130022	0	0
T13	99090	1	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	0	0	0
T22	66543	0	0	0
T120	0	1	0	0
T122	0	1	0	0
T129	0	32281	0	0
T136	0	2	0	0
T152	0	1	0	0
T160	0	32370	0	0
T161	0	1	0	0
T162	0	33112	0	0
T163	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	96922	0	0
T13	99090	2	0	0
T14	66245	0	0	0
T15	32463	0	0	0
T16	97868	0	0	0
T17	99090	0	0	0
T18	8304	0	0	0
T19	2928	0	0	0
T20	1144	0	0	0
T21	33444	2	0	0
T22	66543	0	0	0
T23	0	2	0	0
T62	0	2	0	0
T93	0	1	0	0
T96	0	1	0	0
T97	0	32020	0	0
T98	0	3	0	0
T111	0	1	0	0
T164	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32915197	20554978	0	0
T12	87604	26385	0	0
T13	99090	67050	0	0
T14	66245	32829	0	0
T15	32463	32384	0	0
T16	97868	97813	0	0
T17	99090	33103	0	0
T18	8304	0	0	0
T19	2928	105	0	0
T20	1144	0	0	0
T21	33444	33354	0	0
T22	0	66440	0	0
T23	0	32757	0	0