Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7320	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1067	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1122	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1051	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1059	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1048	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1078	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1145	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1056	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	950	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	932	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1045	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1021	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1097	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1109	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1109	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1206	0	0
adc_en_ctl_rd_A	2147483647	916	0	0
adc_fsm_rst_rd_A	2147483647	932	0	0
adc_intr_ctl_rd_A	2147483647	984	0	0
adc_lp_sample_ctl_rd_A	2147483647	965	0	0
adc_pd_ctl_rd_A	2147483647	1076	0	0
adc_sample_ctl_rd_A	2147483647	1003	0	0
adc_wakeup_ctl_rd_A	2147483647	948	0	0
intr_enable_rd_A	2147483647	1418	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7320	0	0
T1	793301	4	0	0
T2	4351	1	0	0
T3	47255	0	0	0
T4	448599	0	0	0
T5	13643	349	0	0
T6	2690	0	0	0
T25	27182	398	0	0
T26	7978	0	0	0
T27	45302	499	0	0
T28	39928	399	0	0
T63	0	110	0	0
T64	0	384	0	0
T67	0	265	0	0
T70	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1067	0	0
T4	448599	69	0	0
T7	24939	221	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	1	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	11	0	0
T84	0	73	0	0
T165	0	8	0	0
T166	0	49	0	0
T167	0	8	0	0
T168	0	19	0	0
T169	0	40	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1122	0	0
T4	448599	98	0	0
T7	24939	216	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	13	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	8	0	0
T84	0	33	0	0
T165	0	5	0	0
T166	0	45	0	0
T167	0	20	0	0
T168	0	26	0	0
T170	0	14	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1051	0	0
T4	448599	43	0	0
T7	24939	188	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	32	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T69	0	8	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	41	0	0
T84	0	42	0	0
T166	0	8	0	0
T167	0	2	0	0
T168	0	1	0	0
T170	0	26	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1059	0	0
T4	448599	78	0	0
T7	24939	201	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	22	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	5	0	0
T84	0	13	0	0
T166	0	43	0	0
T167	0	3	0	0
T168	0	10	0	0
T169	0	34	0	0
T170	0	11	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1048	0	0
T4	448599	36	0	0
T7	24939	185	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	35	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	14	0	0
T84	0	64	0	0
T165	0	2	0	0
T166	0	25	0	0
T167	0	10	0	0
T168	0	3	0	0
T170	0	16	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1078	0	0
T4	448599	103	0	0
T7	24939	201	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	31	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	3	0	0
T84	0	19	0	0
T165	0	13	0	0
T166	0	30	0	0
T167	0	2	0	0
T168	0	23	0	0
T170	0	28	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1145	0	0
T4	448599	132	0	0
T7	24939	212	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	19	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T69	0	2	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	53	0	0
T84	0	5	0	0
T165	0	5	0	0
T166	0	38	0	0
T167	0	13	0	0
T170	0	7	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1056	0	0
T4	448599	94	0	0
T7	24939	213	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	22	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	13	0	0
T84	0	30	0	0
T166	0	26	0	0
T167	0	3	0	0
T168	0	9	0	0
T169	0	32	0	0
T170	0	8	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	950	0	0
T4	448599	73	0	0
T7	24939	191	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	1	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	10	0	0
T84	0	31	0	0
T166	0	26	0	0
T167	0	10	0	0
T168	0	1	0	0
T169	0	10	0	0
T170	0	13	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	932	0	0
T4	448599	74	0	0
T7	24939	218	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	17	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	5	0	0
T84	0	57	0	0
T165	0	8	0	0
T166	0	17	0	0
T167	0	25	0	0
T168	0	17	0	0
T170	0	2	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1045	0	0
T4	448599	79	0	0
T7	24939	223	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	27	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T69	0	4	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	16	0	0
T84	0	44	0	0
T165	0	9	0	0
T166	0	18	0	0
T167	0	2	0	0
T170	0	7	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1021	0	0
T4	448599	98	0	0
T7	24939	185	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	14	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	20	0	0
T84	0	46	0	0
T165	0	3	0	0
T166	0	10	0	0
T167	0	4	0	0
T168	0	3	0	0
T170	0	22	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1097	0	0
T4	448599	89	0	0
T7	24939	214	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	23	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T69	0	3	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	27	0	0
T84	0	36	0	0
T165	0	1	0	0
T166	0	18	0	0
T167	0	4	0	0
T170	0	17	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1109	0	0
T4	448599	93	0	0
T7	24939	219	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	15	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	17	0	0
T84	0	40	0	0
T165	0	6	0	0
T166	0	24	0	0
T167	0	12	0	0
T168	0	10	0	0
T170	0	11	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1109	0	0
T4	448599	101	0	0
T7	24939	248	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	27	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	25	0	0
T84	0	36	0	0
T165	0	1	0	0
T168	0	8	0	0
T169	0	54	0	0
T170	0	17	0	0
T171	0	19	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1206	0	0
T4	448599	105	0	0
T7	24939	202	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	30	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	40	0	0
T84	0	43	0	0
T165	0	6	0	0
T166	0	20	0	0
T167	0	24	0	0
T168	0	16	0	0
T170	0	31	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	916	0	0
T4	448599	69	0	0
T7	24939	217	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	26	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	11	0	0
T84	0	33	0	0
T165	0	2	0	0
T166	0	21	0	0
T167	0	8	0	0
T168	0	6	0	0
T170	0	6	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	932	0	0
T4	448599	38	0	0
T7	24939	227	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	9	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	7	0	0
T84	0	34	0	0
T165	0	5	0	0
T166	0	42	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	27	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	984	0	0
T4	448599	37	0	0
T7	24939	226	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	26	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	5	0	0
T84	0	19	0	0
T165	0	5	0	0
T166	0	19	0	0
T167	0	4	0	0
T168	0	3	0	0
T170	0	6	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	965	0	0
T4	448599	50	0	0
T7	24939	204	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	11	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	2	0	0
T84	0	61	0	0
T165	0	4	0	0
T166	0	19	0	0
T167	0	8	0	0
T168	0	3	0	0
T170	0	26	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T4	448599	65	0	0
T7	24939	219	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	23	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T69	0	4	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	6	0	0
T84	0	22	0	0
T165	0	2	0	0
T166	0	36	0	0
T167	0	24	0	0
T170	0	32	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1003	0	0
T4	448599	26	0	0
T7	24939	215	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	40	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	7	0	0
T84	0	30	0	0
T165	0	6	0	0
T166	0	50	0	0
T167	0	3	0	0
T168	0	6	0	0
T170	0	24	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	948	0	0
T4	448599	23	0	0
T7	24939	249	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T27	45302	23	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	0	0	0
T76	11173	0	0	0
T78	0	4	0	0
T84	0	54	0	0
T165	0	10	0	0
T166	0	28	0	0
T167	0	3	0	0
T168	0	7	0	0
T170	0	30	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T4	448599	42	0	0
T7	24939	230	0	0
T9	13113	0	0	0
T10	207198	0	0	0
T11	16784	0	0	0
T26	7978	9	0	0
T27	45302	44	0	0
T28	39928	0	0	0
T31	35651	0	0	0
T75	45114	6	0	0
T84	0	32	0	0
T165	0	4	0	0
T172	0	4	0	0
T173	0	19	0	0
T174	0	19	0	0