Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1233131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1187505

1

T1

392

T2

72

T3

325

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2135798	1			T1	195		T2	83		T3	159
values[0x0]	142714	1			T1	108		T2	25		T3	84
values[0x1]	142124	1			T1	90		T2	28		T3	82

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	992637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1427999

1

T1

392

T2

95

T3

325

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15693	1			T1	2		T3	1		T22	4
valid_sources[0x01]	7364	1			T1	1		T3	5		T5	4
valid_sources[0x02]	15415	1			T3	1		T22	1		T5	3
valid_sources[0x03]	8310	1			T1	6		T2	3		T3	1
valid_sources[0x04]	14107	1			T1	1		T22	2		T5	3
valid_sources[0x05]	7173	1			T1	2		T22	1		T5	6
valid_sources[0x06]	9103	1			T1	4		T3	1		T22	3
valid_sources[0x07]	7066	1			T1	1		T5	5		T4	1
valid_sources[0x08]	9820	1			T1	1		T22	1		T4	4
valid_sources[0x09]	23024	1			T1	2		T2	13		T3	1
valid_sources[0x0a]	9731	1			T1	1		T2	10		T3	1
valid_sources[0x0b]	9988	1			T22	3		T5	3		T4	1
valid_sources[0x0c]	7712	1			T1	1		T3	1		T22	3
valid_sources[0x0d]	9895	1			T1	3		T3	1		T22	3
valid_sources[0x0e]	10015	1			T1	5		T3	4		T22	5
valid_sources[0x0f]	7784	1			T1	3		T3	5		T22	1
valid_sources[0x10]	7221	1			T2	6		T3	1		T22	1
valid_sources[0x11]	7220	1			T1	2		T22	3		T5	3
valid_sources[0x12]	21637	1			T1	3		T5	4		T23	2
valid_sources[0x13]	8994	1			T1	2		T3	3		T22	3
valid_sources[0x14]	8110	1			T1	1		T3	1		T5	3
valid_sources[0x15]	7259	1			T1	4		T3	2		T22	2
valid_sources[0x16]	9403	1			T5	1		T4	5		T23	1
valid_sources[0x17]	6807	1			T1	3		T22	5		T5	4
valid_sources[0x18]	11895	1			T3	4		T22	2		T5	2
valid_sources[0x19]	6609	1			T1	4		T3	2		T4	2
valid_sources[0x1a]	7297	1			T1	1		T22	2		T4	5
valid_sources[0x1b]	7864	1			T1	2		T22	1		T5	6
valid_sources[0x1c]	8619	1			T1	3		T22	5		T5	5
valid_sources[0x1d]	8287	1			T3	2		T5	2		T4	1
valid_sources[0x1e]	8701	1			T3	1		T22	1		T5	3
valid_sources[0x1f]	7801	1			T1	1		T5	2		T23	1
valid_sources[0x20]	8180	1			T5	1		T4	1		T23	1
valid_sources[0x21]	7302	1			T3	5		T22	1		T5	3
valid_sources[0x22]	7174	1			T1	1		T3	3		T22	3
valid_sources[0x23]	7126	1			T22	5		T5	4		T4	4
valid_sources[0x24]	7348	1			T1	2		T3	1		T22	4
valid_sources[0x25]	7100	1			T1	1		T22	2		T5	6
valid_sources[0x26]	10902	1			T1	1		T3	4		T22	2
valid_sources[0x27]	10087	1			T1	1		T3	2		T22	2
valid_sources[0x28]	6908	1			T3	4		T22	1		T5	1
valid_sources[0x29]	12370	1			T1	1		T3	1		T5	4
valid_sources[0x2a]	7825	1			T5	3		T4	4		T27	7
valid_sources[0x2b]	10624	1			T1	2		T2	1		T5	2
valid_sources[0x2c]	7541	1			T1	2		T3	1		T22	1
valid_sources[0x2d]	9397	1			T1	2		T3	4		T22	2
valid_sources[0x2e]	10087	1			T22	2		T5	4		T4	4
valid_sources[0x2f]	7130	1			T5	3		T4	1		T6	7
valid_sources[0x30]	11461	1			T2	1		T3	1		T22	3
valid_sources[0x31]	11434	1			T1	1		T3	1		T22	3
valid_sources[0x32]	11310	1			T1	1		T22	1		T5	2
valid_sources[0x33]	7405	1			T1	3		T3	3		T5	4
valid_sources[0x34]	7176	1			T22	1		T5	5		T4	4
valid_sources[0x35]	9715	1			T1	1		T22	2		T5	1
valid_sources[0x36]	7550	1			T3	1		T22	5		T5	3
valid_sources[0x37]	7294	1			T1	3		T3	3		T22	2
valid_sources[0x38]	11281	1			T5	8		T4	1		T7	6
valid_sources[0x39]	6853	1			T3	1		T22	3		T5	2
valid_sources[0x3a]	9660	1			T1	1		T5	3		T4	3
valid_sources[0x3b]	9815	1			T1	1		T3	1		T22	2
valid_sources[0x3c]	7034	1			T1	1		T3	1		T22	4
valid_sources[0x3d]	12705	1			T1	2		T22	3		T5	7
valid_sources[0x3e]	8239	1			T1	2		T22	2		T5	4
valid_sources[0x3f]	7596	1			T1	7		T22	6		T4	2
valid_sources[0x40]	7078	1			T1	3		T22	2		T5	3
valid_sources[0x41]	7192	1			T22	1		T5	1		T4	5
valid_sources[0x42]	11068	1			T1	4		T3	2		T22	2
valid_sources[0x43]	6660	1			T1	6		T3	1		T22	3
valid_sources[0x44]	12097	1			T1	1		T3	2		T22	1
valid_sources[0x45]	7250	1			T5	3		T4	1		T6	11
valid_sources[0x46]	7540	1			T1	8		T3	2		T22	1
valid_sources[0x47]	8369	1			T2	3		T3	4		T22	3
valid_sources[0x48]	11412	1			T2	6		T3	2		T22	4
valid_sources[0x49]	6776	1			T1	1		T3	1		T5	7
valid_sources[0x4a]	9309	1			T2	16		T3	1		T22	3
valid_sources[0x4b]	7563	1			T1	1		T2	12		T5	6
valid_sources[0x4c]	7537	1			T3	1		T5	3		T4	2
valid_sources[0x4d]	9337	1			T1	1		T3	3		T22	1
valid_sources[0x4e]	9515	1			T1	5		T3	1		T22	1
valid_sources[0x4f]	7355	1			T1	2		T3	5		T22	3
valid_sources[0x50]	9504	1			T1	2		T22	1		T5	2
valid_sources[0x51]	7315	1			T1	2		T3	4		T22	4
valid_sources[0x52]	14944	1			T1	1		T3	2		T5	4
valid_sources[0x53]	9611	1			T1	2		T22	2		T5	2
valid_sources[0x54]	7198	1			T3	1		T22	3		T4	10
valid_sources[0x55]	7678	1			T1	2		T3	3		T22	4
valid_sources[0x56]	7089	1			T2	2		T3	1		T22	2
valid_sources[0x57]	9930	1			T1	1		T2	3		T5	2
valid_sources[0x58]	8951	1			T3	1		T22	1		T5	5
valid_sources[0x59]	8303	1			T1	4		T3	1		T5	6
valid_sources[0x5a]	7062	1			T22	4		T5	4		T4	3
valid_sources[0x5b]	6992	1			T1	1		T3	1		T22	1
valid_sources[0x5c]	11564	1			T1	4		T22	1		T5	1
valid_sources[0x5d]	7192	1			T1	2		T5	1		T4	2
valid_sources[0x5e]	8306	1			T1	1		T2	3		T3	2
valid_sources[0x5f]	8341	1			T1	3		T3	3		T22	1
valid_sources[0x60]	8061	1			T22	3		T5	1		T4	5
valid_sources[0x61]	11205	1			T3	4		T22	4		T5	4
valid_sources[0x62]	7910	1			T1	2		T3	1		T5	1
valid_sources[0x63]	11432	1			T1	1		T22	3		T5	1
valid_sources[0x64]	7007	1			T1	1		T4	3		T27	2
valid_sources[0x65]	7091	1			T1	1		T3	4		T22	4
valid_sources[0x66]	7752	1			T2	8		T22	2		T5	4
valid_sources[0x67]	11937	1			T3	1		T22	4		T5	3
valid_sources[0x68]	10157	1			T5	1		T4	1		T24	1
valid_sources[0x69]	9936	1			T1	4		T22	2		T5	2
valid_sources[0x6a]	7209	1			T1	3		T22	2		T5	4
valid_sources[0x6b]	16790	1			T1	2		T3	3		T5	4
valid_sources[0x6c]	12017	1			T1	4		T3	2		T22	2
valid_sources[0x6d]	11210	1			T1	1		T22	1		T4	3
valid_sources[0x6e]	11317	1			T3	1		T22	3		T5	4
valid_sources[0x6f]	7461	1			T3	6		T5	1		T4	1
valid_sources[0x70]	7001	1			T1	2		T3	4		T5	7
valid_sources[0x71]	7431	1			T5	3		T23	1		T6	6
valid_sources[0x72]	7133	1			T2	6		T3	2		T22	1
valid_sources[0x73]	7099	1			T1	2		T5	7		T4	1
valid_sources[0x74]	7539	1			T22	4		T5	3		T4	6
valid_sources[0x75]	6952	1			T1	4		T22	1		T5	5
valid_sources[0x76]	7043	1			T1	1		T2	1		T3	6
valid_sources[0x77]	11256	1			T1	4		T3	2		T22	2
valid_sources[0x78]	7137	1			T1	1		T3	2		T5	2
valid_sources[0x79]	7323	1			T1	3		T3	1		T5	1
valid_sources[0x7a]	11375	1			T1	8		T2	8		T3	2
valid_sources[0x7b]	7311	1			T3	1		T22	1		T5	7
valid_sources[0x7c]	7908	1			T22	1		T5	2		T4	1
valid_sources[0x7d]	11463	1			T22	5		T5	7		T4	4
valid_sources[0x7e]	9927	1			T1	1		T22	1		T4	5
valid_sources[0x7f]	7641	1			T3	1		T22	2		T5	5
valid_sources[0x80]	7590	1			T22	2		T5	2		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063499

1

T1

195

T2

28

T3

159

values[0x0]

all_enables

biggest_size

72137

1

T1

107

T2

23

T3

84

values[0x1]

all_enables

biggest_size

51869

1

T1

90

T2

21

T3

82