Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27349	1			T1	327		T2	8		T3	348
auto[PWRUP]	102	1			T33	1		T34	5		T182	1
auto[ONEST_0]	56	1			T19	2		T34	1		T182	2
auto[ONEST_021]	13	1			T124	1		T45	2		T183	1
auto[ONEST_1]	59	1			T182	1		T184	2		T185	3
auto[ONEST_DONE]	3	1			T186	1		T187	1		T188	1
auto[LP_0]	117	1			T19	1		T33	1		T34	1
auto[LP_021]	29	1			T189	1		T45	1		T183	1
auto[LP_1]	111	1			T19	2		T33	4		T182	1
auto[LP_EVAL]	63	1			T33	1		T130	1		T189	4
auto[LP_SLP]	421	1			T19	5		T33	7		T34	4
auto[LP_PWRUP]	28	1			T182	1		T130	1		T45	1
auto[NP_0]	141	1			T33	2		T34	2		T182	2
auto[NP_021]	27	1			T33	2		T189	2		T124	1
auto[NP_1]	124	1			T182	3		T130	3		T184	2
auto[NP_EVAL]	30	1			T189	2		T45	1		T190	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T45

1

T190

1

T191

1

min

26831

1

T1

327

T2

8

T3

348

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26836	1			T1	327		T2	8		T3	348
pow[0x1]	8	1			T130	1		T47	1		T192	1
pow[0x2]	17	1			T189	1		T45	1		T47	2
pow[0x3]	22	1			T184	1		T193	1		T194	2
pow[0x4]	54	1			T33	1		T34	1		T182	1
pow[0x5]	113	1			T19	2		T33	1		T34	2
pow[0x6]	222	1			T19	1		T34	7		T182	5
pow[0x7]	474	1			T19	2		T33	11		T34	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

182

1

T19

2

T34

1

T182

1

min

26433

1

T1

327

T2

8

T3

348

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26433	1			T1	327		T2	8		T3	348
pow[0x5]	1	1			T195	1		-	-		-	-
pow[0x6]	3	1			T196	1		T191	1		T197	1
pow[0x7]	2	1			T198	1		T199	1		-	-
pow[0x8]	5	1			T184	1		T193	1		T200	1
pow[0x9]	5	1			T124	1		T201	1		T188	1
pow[0xa]	20	1			T34	1		T130	1		T189	1
pow[0xb]	40	1			T130	3		T47	1		T190	1
pow[0xc]	61	1			T19	1		T33	2		T130	1
pow[0xd]	110	1			T19	1		T33	5		T130	2
pow[0xe]	242	1			T33	6		T34	2		T182	4
pow[0xf]	529	1			T19	4		T33	9		T34	2