Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2107	1			T2	1		T4	1		T23	2
auto[PWRUP]	117	1			T19	1		T33	2		T34	1
auto[ONEST_0]	65	1			T19	2		T33	2		T34	3
auto[ONEST_021]	9	1			T251	1		T310	1		T196	1
auto[ONEST_1]	86	1			T19	2		T83	1		T33	1
auto[ONEST_DONE]	6	1			T340	1		T201	1		T341	2
auto[LP_0]	101	1			T33	2		T34	3		T130	1
auto[LP_021]	33	1			T184	1		T124	1		T183	2
auto[LP_1]	127	1			T33	3		T182	1		T130	1
auto[LP_EVAL]	52	1			T19	2		T33	2		T130	1
auto[LP_SLP]	476	1			T33	9		T169	1		T34	1
auto[LP_PWRUP]	30	1			T19	1		T34	1		T182	1
auto[NP_0]	206	1			T10	2		T12	1		T19	2
auto[NP_021]	53	1			T10	2		T12	1		T130	2
auto[NP_1]	211	1			T12	3		T19	2		T83	1
auto[NP_EVAL]	35	1			T83	2		T34	1		T182	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T33

1

T47

1

T342

1

min

1875

1

T2

1

T4

1

T23

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1885	1			T2	1		T4	1		T23	2
pow[0x1]	9	1			T47	2		T194	1		T251	2
pow[0x2]	20	1			T34	1		T184	1		T193	1
pow[0x3]	31	1			T33	1		T182	1		T189	1
pow[0x4]	62	1			T19	1		T33	1		T34	1
pow[0x5]	124	1			T33	2		T34	5		T182	2
pow[0x6]	203	1			T19	6		T33	3		T34	2
pow[0x7]	476	1			T19	6		T33	8		T34	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

162

1

T19

2

T33

3

T34

2

min

1313

1

T2

1

T4

1

T23

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1316	1			T2	1		T4	1		T23	2
pow[0x1]	14	1			T102	1		T103	1		T131	3
pow[0x2]	37	1			T10	1		T130	7		T110	4
pow[0x3]	40	1			T10	1		T103	3		T96	1
pow[0x4]	58	1			T10	2		T12	1		T83	3
pow[0x7]	2	1			T244	1		T343	1		-	-
pow[0x8]	3	1			T344	1		T197	1		T345	1
pow[0x9]	8	1			T184	1		T244	1		T346	2
pow[0xa]	17	1			T34	1		T182	1		T185	1
pow[0xb]	27	1			T182	1		T185	2		T189	1
pow[0xc]	63	1			T33	2		T182	1		T130	1
pow[0xd]	125	1			T33	2		T34	1		T182	3
pow[0xe]	262	1			T19	1		T33	4		T34	2
pow[0xf]	549	1			T19	6		T33	9		T34	6