Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T9,T10,T11
1	Covered	T9,T16,T19

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T9,T10,T11
1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T20
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T20
0	1	Covered	T10,T11,T20
1	0	Covered	T10,T11,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T19
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T10,T14,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T11,T12,T14
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T14
0	1	Covered	T11,T12,T14
1	0	Covered	T11,T12,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T20
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T11,T12
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T20
0	1	Covered	T10,T14,T20
1	0	Covered	T10,T14,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T15,T19
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T19
0	1	Covered	T14,T15,T19
1	0	Covered	T14,T15,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T10,T19,T20
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T11,T13
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T19,T20
0	1	Covered	T10,T19,T20
1	0	Covered	T10,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T9,T11,T13
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T12

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T13
1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T19
1	0	Covered	T9,T11,T12
1	1	Covered	T9,T10,T11

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T10,T11,T13

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T19
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T19
0	1	Covered	T10,T11,T19
1	0	Covered	T10,T11,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T19
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T10,T14,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T11,T12,T14
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T14
0	1	Covered	T11,T12,T14
1	0	Covered	T11,T12,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T20
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T11,T12
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T20
0	1	Covered	T10,T14,T20
1	0	Covered	T10,T14,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T15,T19
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T19
0	1	Covered	T14,T15,T19
1	0	Covered	T14,T15,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T10,T19,T20
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T11,T13
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T19,T20
0	1	Covered	T10,T19,T20
1	0	Covered	T10,T19,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T9,T11,T13
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T12

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T13
1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T19
1	0	Covered	T9,T11,T12
1	1	Covered	T9,T10,T11

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T10,T11,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T10,T12,T13
1	1	0	Covered	T10,T12,T13
1	1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T12,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T10,T11,T13
1	1	0	Covered	T10,T11,T13
1	1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T10,T11,T13
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T12

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T10,T13,T18
1	1	0	Covered	T10,T12,T13
1	1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T12,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T10,T11,T13
1	1	0	Covered	T10,T11,T13
1	1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T11,T13

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T11,T13,T14
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T11,T13,T14
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T9,T10,T11
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T11
1	0	1	Covered	T13,T14,T18
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T9,T10,T11
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T10,T12,T13
1	0	Covered	T9,T10,T11

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T9,T10,T11
1	1	Covered	T10,T12,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T12,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T12,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T12,T13

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T16,T19
0	1	Covered	T9,T10,T11
0	0	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T14,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T14,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T11,T12,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T11,T12,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T14,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T14,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T14,T15,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T14,T15,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T19,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T13

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T10,T11,T13

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32512662	32230560	0	0
gen_filter_match[0].MatchCheck00_A	32512662	9442277	0	0
gen_filter_match[0].MatchCheck01_A	32512662	2423162	0	0
gen_filter_match[0].MatchCheck10_A	32512662	2809399	0	0
gen_filter_match[0].MatchCheck11_A	32512662	17555722	0	0
gen_filter_match[1].MatchCheck00_A	32512662	11138064	0	0
gen_filter_match[1].MatchCheck01_A	32512662	1264187	0	0
gen_filter_match[1].MatchCheck10_A	32512662	1232315	0	0
gen_filter_match[1].MatchCheck11_A	32512662	18595994	0	0
gen_filter_match[2].MatchCheck00_A	32512662	11675184	0	0
gen_filter_match[2].MatchCheck01_A	32512662	799774	0	0
gen_filter_match[2].MatchCheck10_A	32512662	479324	0	0
gen_filter_match[2].MatchCheck11_A	32512662	19276278	0	0
gen_filter_match[3].MatchCheck00_A	32512662	11892739	0	0
gen_filter_match[3].MatchCheck01_A	32512662	297284	0	0
gen_filter_match[3].MatchCheck10_A	32512662	336389	0	0
gen_filter_match[3].MatchCheck11_A	32512662	19704148	0	0
gen_filter_match[4].MatchCheck00_A	32512662	11306990	0	0
gen_filter_match[4].MatchCheck01_A	32512662	3	0	0
gen_filter_match[4].MatchCheck10_A	32512662	100848	0	0
gen_filter_match[4].MatchCheck11_A	32512662	20822719	0	0
gen_filter_match[5].MatchCheck00_A	32512662	11863953	0	0
gen_filter_match[5].MatchCheck01_A	32512662	32709	0	0
gen_filter_match[5].MatchCheck10_A	32512662	121	0	0
gen_filter_match[5].MatchCheck11_A	32512662	20333777	0	0
gen_filter_match[6].MatchCheck00_A	32512662	12207670	0	0
gen_filter_match[6].MatchCheck01_A	32512662	69241	0	0
gen_filter_match[6].MatchCheck10_A	32512662	99929	0	0
gen_filter_match[6].MatchCheck11_A	32512662	19853720	0	0
gen_filter_match[7].MatchCheck00_A	32512662	11882170	0	0
gen_filter_match[7].MatchCheck01_A	32512662	147073	0	0
gen_filter_match[7].MatchCheck10_A	32512662	194639	0	0
gen_filter_match[7].MatchCheck11_A	32512662	20006678	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	32230560	0	0
T9	649	597	0	0
T10	66822	66283	0	0
T11	41646	41399	0	0
T12	43950	43291	0	0
T13	32985	32926	0	0
T14	64992	64920	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	9442277	0	0
T9	649	597	0	0
T10	66822	36	0	0
T11	41646	41399	0	0
T12	43950	40	0	0
T13	32985	4	0	0
T14	64992	64920	0	0
T15	32445	3	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	2423162	0	0
T19	47794	33070	0	0
T20	66039	0	0	0
T21	99678	0	0	0
T36	58	0	0	0
T37	81	0	0	0
T52	64811	0	0	0
T83	21446	0	0	0
T84	1206	0	0	0
T89	100119	33304	0	0
T90	0	33502	0	0
T91	0	33150	0	0
T92	0	33723	0	0
T93	0	34299	0	0
T94	0	33101	0	0
T95	0	31720	0	0
T96	0	8205	0	0
T97	0	32657	0	0
T98	4395	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	2809399	0	0
T15	32445	32356	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	0	0	0
T19	47794	0	0	0
T20	66039	0	0	0
T21	99678	32771	0	0
T36	58	0	0	0
T52	0	32151	0	0
T84	1206	0	0	0
T98	4395	0	0	0
T99	0	32541	0	0
T100	0	33624	0	0
T101	0	33629	0	0
T102	0	2620	0	0
T103	0	10	0	0
T104	0	1	0	0
T105	0	32665	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	17555722	0	0
T10	66822	66247	0	0
T11	41646	0	0	0
T12	43950	43251	0	0
T13	32985	32922	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98188	0	0
T19	0	339	0	0
T20	0	32827	0	0
T21	0	33595	0	0
T26	92	0	0	0
T52	0	32606	0	0
T53	0	63858	0	0
T106	0	98314	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11138064	0	0
T9	649	597	0	0
T10	66822	36	0	0
T11	41646	8494	0	0
T12	43950	43291	0	0
T13	32985	4	0	0
T14	64992	64920	0	0
T15	32445	3	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	1264187	0	0
T20	66039	32827	0	0
T21	99678	0	0	0
T36	58	0	0	0
T37	81	0	0	0
T50	0	32719	0	0
T52	64811	0	0	0
T53	63950	32327	0	0
T83	21446	0	0	0
T98	4395	0	0	0
T106	98391	0	0	0
T107	0	33029	0	0
T108	0	32665	0	0
T109	0	32673	0	0
T110	0	698	0	0
T111	0	32731	0	0
T112	0	36825	0	0
T113	0	6900	0	0
T114	4709	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	1232315	0	0
T11	41646	1	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	0	0	0
T19	47794	0	0	0
T26	92	0	0	0
T52	0	32606	0	0
T83	0	20175	0	0
T93	0	32668	0	0
T103	0	8	0	0
T104	0	1	0	0
T106	0	33210	0	0
T115	0	32302	0	0
T116	0	32688	0	0
T117	0	31940	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	18595994	0	0
T10	66822	66247	0	0
T11	41646	32904	0	0
T12	43950	0	0	0
T13	32985	32922	0	0
T14	64992	0	0	0
T15	32445	32356	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98188	0	0
T21	0	99618	0	0
T26	92	0	0	0
T53	0	31531	0	0
T118	0	32626	0	0
T119	0	34063	0	0
T120	0	71443	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11675184	0	0
T9	649	597	0	0
T10	66822	52300	0	0
T11	41646	8494	0	0
T12	43950	43291	0	0
T13	32985	4	0	0
T14	64992	4	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	799774	0	0
T92	33776	0	0	0
T104	65638	1	0	0
T105	97799	0	0	0
T117	98233	0	0	0
T121	33474	33383	0	0
T122	0	32555	0	0
T123	0	33270	0	0
T124	0	32629	0	0
T125	0	33723	0	0
T126	0	32726	0	0
T127	0	32084	0	0
T128	0	33205	0	0
T129	0	33077	0	0
T130	95980	0	0	0
T131	20860	0	0	0
T132	65923	0	0	0
T133	32244	0	0	0
T134	32442	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	479324	0	0
T11	41646	1	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	0	0	0
T19	47794	0	0	0
T26	92	0	0	0
T104	0	1	0	0
T124	0	1	0	0
T135	0	33089	0	0
T136	0	1	0	0
T137	0	32750	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	32444	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	19276278	0	0
T10	66822	13983	0	0
T11	41646	32904	0	0
T12	43950	0	0	0
T13	32985	32922	0	0
T14	64992	64916	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98188	0	0
T20	0	33109	0	0
T21	0	32771	0	0
T26	92	0	0	0
T52	0	32606	0	0
T53	0	63858	0	0
T83	0	20175	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11892739	0	0
T9	649	597	0	0
T10	66822	52300	0	0
T11	41646	8494	0	0
T12	43950	40	0	0
T13	32985	4	0	0
T14	64992	64920	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	297284	0	0
T48	0	33401	0	0
T89	100119	1	0	0
T90	33557	0	0	0
T111	0	33041	0	0
T115	65938	0	0	0
T116	32777	0	0	0
T117	0	1	0	0
T140	0	1	0	0
T142	0	32336	0	0
T143	0	1	0	0
T144	0	32205	0	0
T145	0	645	0	0
T146	0	1	0	0
T147	32786	0	0	0
T148	33121	0	0	0
T149	614	0	0	0
T150	99605	0	0	0
T151	65372	0	0	0
T152	33081	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	336389	0	0
T11	41646	1	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	1	0	0
T19	47794	0	0	0
T26	92	0	0	0
T89	0	1	0	0
T116	0	1	0	0
T117	0	2	0	0
T132	0	32945	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T153	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	19704148	0	0
T10	66822	13983	0	0
T11	41646	32904	0	0
T12	43950	43251	0	0
T13	32985	32922	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98187	0	0
T20	0	33109	0	0
T21	0	33252	0	0
T26	92	0	0	0
T52	0	64757	0	0
T53	0	63858	0	0
T83	0	20175	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11306990	0	0
T9	649	597	0	0
T10	66822	52300	0	0
T11	41646	41399	0	0
T12	43950	40	0	0
T13	32985	4	0	0
T14	64992	64920	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	3	0	0
T146	97198	1	0	0
T154	99122	1	0	0
T155	0	1	0	0
T156	33250	0	0	0
T157	64042	0	0	0
T158	6459	0	0	0
T159	97700	0	0	0
T160	6568	0	0	0
T161	66142	0	0	0
T162	6974	0	0	0
T163	33172	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	100848	0	0
T18	98272	1	0	0
T19	47794	0	0	0
T20	66039	0	0	0
T21	99678	0	0	0
T36	58	0	0	0
T37	81	0	0	0
T52	64811	0	0	0
T83	21446	0	0	0
T84	1206	0	0	0
T89	0	1	0	0
T98	4395	0	0	0
T103	0	4	0	0
T104	0	1	0	0
T106	0	32555	0	0
T117	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T153	0	1	0	0
T164	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	20822719	0	0
T10	66822	13983	0	0
T11	41646	0	0	0
T12	43950	43251	0	0
T13	32985	32922	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98187	0	0
T19	0	33070	0	0
T21	0	33252	0	0
T26	92	0	0	0
T52	0	64757	0	0
T83	0	20175	0	0
T118	0	32330	0	0
T119	0	66925	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11863953	0	0
T9	649	597	0	0
T10	66822	14019	0	0
T11	41646	8494	0	0
T12	43950	43291	0	0
T13	32985	4	0	0
T14	64992	64920	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	32709	0	0
T89	100119	1	0	0
T90	33557	0	0	0
T115	65938	0	0	0
T116	32777	0	0	0
T117	0	1	0	0
T141	0	1	0	0
T146	0	1	0	0
T147	32786	0	0	0
T148	33121	0	0	0
T149	614	0	0	0
T150	99605	0	0	0
T151	65372	0	0	0
T152	33081	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	32702	0	0
T168	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	121	0	0
T11	41646	1	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	1	0	0
T19	47794	0	0	0
T20	0	1	0	0
T26	92	0	0	0
T89	0	1	0	0
T100	0	1	0	0
T116	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	20333777	0	0
T10	66822	52264	0	0
T11	41646	32904	0	0
T12	43950	0	0	0
T13	32985	32922	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98187	0	0
T20	0	33108	0	0
T26	92	0	0	0
T52	0	32151	0	0
T53	0	63858	0	0
T83	0	20175	0	0
T120	0	33409	0	0
T170	0	32455	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	12207670	0	0
T9	649	597	0	0
T10	66822	52300	0	0
T11	41646	8494	0	0
T12	43950	43291	0	0
T13	32985	4	0	0
T14	64992	4	0	0
T15	32445	3	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	69241	0	0
T20	66039	1	0	0
T21	99678	0	0	0
T36	58	0	0	0
T37	81	0	0	0
T52	64811	0	0	0
T83	21446	0	0	0
T89	100119	1	0	0
T98	4395	0	0	0
T115	65938	0	0	0
T141	0	1	0	0
T143	0	1	0	0
T147	32786	0	0	0
T155	0	1	0	0
T171	0	1	0	0
T172	0	36856	0	0
T173	0	32379	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	99929	0	0
T11	41646	1	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	1	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	1	0	0
T19	47794	0	0	0
T20	0	1	0	0
T26	92	0	0	0
T89	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0
T151	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	19853720	0	0
T10	66822	13983	0	0
T11	41646	32904	0	0
T12	43950	0	0	0
T13	32985	32922	0	0
T14	64992	64915	0	0
T15	32445	32356	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98187	0	0
T19	0	33070	0	0
T20	0	32826	0	0
T21	0	33595	0	0
T26	92	0	0	0
T83	0	20175	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	11882170	0	0
T9	649	597	0	0
T10	66822	52300	0	0
T11	41646	41399	0	0
T12	43950	40	0	0
T13	32985	4	0	0
T14	64992	4	0	0
T15	32445	32359	0	0
T16	1180	1095	0	0
T17	5641	5591	0	0
T26	92	8	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	147073	0	0
T10	66822	13983	0	0
T11	41646	0	0	0
T12	43950	0	0	0
T13	32985	0	0	0
T14	64992	0	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	0	0	0
T20	0	1	0	0
T26	92	0	0	0
T117	0	1	0	0
T125	0	1	0	0
T140	0	32866	0	0
T151	0	1	0	0
T170	0	32632	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	33909	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	194639	0	0
T14	64992	1	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	1	0	0
T19	47794	0	0	0
T20	66039	1	0	0
T21	99678	0	0	0
T84	1206	0	0	0
T89	0	1	0	0
T98	4395	0	0	0
T100	0	1	0	0
T115	0	33412	0	0
T136	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T174	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32512662	20006678	0	0
T12	43950	43251	0	0
T13	32985	32922	0	0
T14	64992	64915	0	0
T15	32445	0	0	0
T16	1180	0	0	0
T17	5641	0	0	0
T18	98272	98187	0	0
T19	47794	33070	0	0
T20	0	32826	0	0
T21	0	66023	0	0
T26	92	0	0	0
T52	0	64757	0	0
T83	0	20175	0	0
T84	1206	0	0	0
T106	0	33210	0	0