Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6041	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1451	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1350	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1362	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1485	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1423	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1421	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1418	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1353	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1322	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1352	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1454	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1303	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1253	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1372	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1341	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1394	0	0
adc_en_ctl_rd_A	2147483647	1270	0	0
adc_fsm_rst_rd_A	2147483647	1172	0	0
adc_intr_ctl_rd_A	2147483647	1148	0	0
adc_lp_sample_ctl_rd_A	2147483647	1085	0	0
adc_pd_ctl_rd_A	2147483647	1237	0	0
adc_sample_ctl_rd_A	2147483647	1028	0	0
adc_wakeup_ctl_rd_A	2147483647	1044	0	0
intr_enable_rd_A	2147483647	1561	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6041	0	0
T2	3990	1	0	0
T3	62642	0	0	0
T4	31834	0	0	0
T5	53738	0	0	0
T6	103778	2	0	0
T7	7258	0	0	0
T22	9931	243	0	0
T23	33345	0	0	0
T24	16243	481	0	0
T25	5839	0	0	0
T30	0	1	0	0
T35	0	243	0	0
T55	0	187	0	0
T56	0	239	0	0
T57	0	148	0	0
T58	0	131	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1451	0	0
T1	78489	15	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	46	0	0
T5	53738	65	0	0
T6	103778	56	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	8	0	0
T25	5839	0	0	0
T28	0	57	0	0
T30	0	46	0	0
T35	0	7	0	0
T65	0	8	0	0
T178	0	5	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1350	0	0
T1	78489	27	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	8	0	0
T5	53738	58	0	0
T6	103778	42	0	0
T7	0	5	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	2	0	0
T25	5839	0	0	0
T28	0	21	0	0
T30	0	83	0	0
T35	0	1	0	0
T65	0	6	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1362	0	0
T1	78489	4	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	85	0	0
T5	53738	69	0	0
T6	103778	33	0	0
T7	0	16	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	8	0	0
T25	5839	0	0	0
T28	0	10	0	0
T30	0	47	0	0
T178	0	12	0	0
T179	0	9	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1485	0	0
T1	78489	27	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	42	0	0
T5	53738	66	0	0
T6	103778	69	0	0
T7	0	25	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	24	0	0
T25	5839	0	0	0
T28	0	96	0	0
T30	0	63	0	0
T55	0	1	0	0
T65	0	1	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1423	0	0
T1	78489	25	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	63	0	0
T5	53738	93	0	0
T6	103778	56	0	0
T7	0	19	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	7	0	0
T25	5839	0	0	0
T28	0	32	0	0
T30	0	46	0	0
T35	0	8	0	0
T65	0	4	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T1	78489	13	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	44	0	0
T5	53738	39	0	0
T6	103778	52	0	0
T7	0	5	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	5	0	0
T25	5839	0	0	0
T28	0	54	0	0
T30	0	60	0	0
T55	0	8	0	0
T65	0	8	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T1	78489	3	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	66	0	0
T5	53738	52	0	0
T6	103778	24	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	1	0	0
T25	5839	0	0	0
T28	0	35	0	0
T30	0	61	0	0
T35	0	5	0	0
T55	0	14	0	0
T65	0	14	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1353	0	0
T1	78489	13	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	17	0	0
T5	53738	24	0	0
T6	103778	48	0	0
T7	0	18	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	6	0	0
T25	5839	0	0	0
T28	0	30	0	0
T30	0	58	0	0
T35	0	7	0	0
T65	0	14	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322	0	0
T1	78489	6	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	42	0	0
T5	53738	30	0	0
T6	103778	35	0	0
T7	0	9	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	5	0	0
T25	5839	0	0	0
T28	0	37	0	0
T30	0	75	0	0
T55	0	8	0	0
T65	0	14	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1352	0	0
T1	78489	26	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	24	0	0
T5	53738	56	0	0
T6	103778	36	0	0
T7	0	9	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	10	0	0
T25	5839	0	0	0
T28	0	77	0	0
T30	0	49	0	0
T55	0	5	0	0
T65	0	12	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1454	0	0
T1	78489	11	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	41	0	0
T5	53738	85	0	0
T6	103778	41	0	0
T7	0	10	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	9	0	0
T25	5839	0	0	0
T28	0	60	0	0
T30	0	36	0	0
T55	0	17	0	0
T65	0	6	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T1	78489	2	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	12	0	0
T5	53738	69	0	0
T6	103778	48	0	0
T7	0	20	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	19	0	0
T25	5839	0	0	0
T28	0	52	0	0
T30	0	39	0	0
T55	0	8	0	0
T65	0	4	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1253	0	0
T1	78489	41	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	40	0	0
T5	53738	60	0	0
T6	103778	33	0	0
T7	0	31	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	4	0	0
T25	5839	0	0	0
T28	0	46	0	0
T30	0	24	0	0
T35	0	8	0	0
T55	0	2	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T1	78489	11	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	26	0	0
T5	53738	57	0	0
T6	103778	70	0	0
T7	0	6	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	20	0	0
T25	5839	0	0	0
T28	0	49	0	0
T30	0	52	0	0
T55	0	6	0	0
T178	0	21	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1341	0	0
T1	78489	8	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	51	0	0
T5	53738	49	0	0
T6	103778	64	0	0
T7	0	7	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	4	0	0
T25	5839	0	0	0
T28	0	63	0	0
T30	0	54	0	0
T55	0	12	0	0
T65	0	10	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1394	0	0
T4	31834	62	0	0
T5	53738	62	0	0
T6	103778	27	0	0
T7	7258	13	0	0
T8	256480	0	0	0
T23	33345	0	0	0
T24	16243	5	0	0
T25	5839	0	0	0
T28	0	63	0	0
T29	65933	0	0	0
T30	0	39	0	0
T35	8934	0	0	0
T55	0	2	0	0
T65	0	2	0	0
T179	0	8	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1270	0	0
T1	78489	7	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	64	0	0
T5	53738	43	0	0
T6	103778	28	0	0
T7	0	3	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	16	0	0
T25	5839	0	0	0
T28	0	35	0	0
T30	0	51	0	0
T55	0	16	0	0
T178	0	7	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1172	0	0
T1	78489	14	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	40	0	0
T5	53738	61	0	0
T6	103778	12	0	0
T7	0	5	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	0	0	0
T25	5839	0	0	0
T28	0	61	0	0
T30	0	8	0	0
T55	0	5	0	0
T178	0	4	0	0
T179	0	2	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1148	0	0
T1	78489	16	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	43	0	0
T5	53738	65	0	0
T6	103778	10	0	0
T7	0	8	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	16	0	0
T25	5839	0	0	0
T28	0	46	0	0
T30	0	26	0	0
T55	0	2	0	0
T65	0	4	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1085	0	0
T1	78489	10	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	73	0	0
T5	53738	46	0	0
T6	103778	23	0	0
T7	0	1	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	9	0	0
T25	5839	0	0	0
T28	0	28	0	0
T30	0	36	0	0
T178	0	3	0	0
T179	0	3	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1237	0	0
T1	78489	8	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	33	0	0
T5	53738	52	0	0
T6	103778	51	0	0
T7	0	5	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	33	0	0
T25	5839	0	0	0
T28	0	64	0	0
T30	0	39	0	0
T35	0	10	0	0
T55	0	13	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1028	0	0
T1	78489	8	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	7	0	0
T5	53738	59	0	0
T6	103778	11	0	0
T7	0	7	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	8	0	0
T25	5839	0	0	0
T28	0	17	0	0
T30	0	40	0	0
T55	0	13	0	0
T65	0	3	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1044	0	0
T1	78489	10	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	41	0	0
T5	53738	51	0	0
T6	103778	33	0	0
T7	0	6	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	10	0	0
T25	5839	0	0	0
T28	0	33	0	0
T30	0	34	0	0
T55	0	12	0	0
T178	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T1	78489	15	0	0
T2	3990	0	0	0
T3	62642	0	0	0
T4	31834	31	0	0
T5	53738	54	0	0
T6	103778	19	0	0
T7	0	4	0	0
T22	9931	0	0	0
T23	33345	0	0	0
T24	16243	2	0	0
T25	5839	5	0	0
T28	0	37	0	0
T30	0	33	0	0
T55	0	6	0	0