Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1220274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1172223

1

T5

175

T1

283

T6

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2106255	1			T5	48		T1	481		T6	19
values[0x0]	142840	1			T5	63		T1	133		T6	9
values[0x1]	143402	1			T5	93		T1	151		T6	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	982235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1410262

1

T5

193

T1

457

T6

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11377	1			T1	2		T2	3		T4	1
valid_sources[0x01]	6870	1			T1	2		T2	5		T26	1
valid_sources[0x02]	7354	1			T5	6		T1	3		T2	1
valid_sources[0x03]	6792	1			T1	3		T2	4		T7	1
valid_sources[0x04]	7862	1			T5	1		T1	6		T2	4
valid_sources[0x05]	11371	1			T1	2		T44	2		T9	26
valid_sources[0x06]	7127	1			T5	4		T1	3		T2	5
valid_sources[0x07]	6718	1			T5	1		T1	1		T2	1
valid_sources[0x08]	20576	1			T1	3		T4	1		T7	2
valid_sources[0x09]	6745	1			T1	1		T2	7		T26	1
valid_sources[0x0a]	12023	1			T5	1		T1	3		T2	2
valid_sources[0x0b]	11551	1			T1	2		T2	1		T44	3
valid_sources[0x0c]	6684	1			T5	2		T1	3		T2	1
valid_sources[0x0d]	14034	1			T5	1		T1	2		T2	6
valid_sources[0x0e]	7065	1			T2	3		T3	4		T30	1
valid_sources[0x0f]	7723	1			T5	1		T1	5		T2	1
valid_sources[0x10]	14254	1			T5	6		T1	1		T2	3
valid_sources[0x11]	9267	1			T1	1		T2	1		T4	1
valid_sources[0x12]	15082	1			T1	1		T2	2		T7	1
valid_sources[0x13]	15114	1			T1	1		T7	2		T44	2
valid_sources[0x14]	7038	1			T1	4		T2	1		T4	1
valid_sources[0x15]	9397	1			T5	3		T1	3		T2	3
valid_sources[0x16]	6724	1			T5	1		T1	3		T30	1
valid_sources[0x17]	6807	1			T1	5		T2	3		T30	1
valid_sources[0x18]	14738	1			T5	3		T1	5		T2	3
valid_sources[0x19]	7722	1			T2	1		T4	1		T7	2
valid_sources[0x1a]	7304	1			T1	8		T2	8		T26	1
valid_sources[0x1b]	9035	1			T5	2		T1	3		T2	2
valid_sources[0x1c]	14641	1			T1	1		T2	4		T7	4
valid_sources[0x1d]	7010	1			T1	2		T2	1		T7	1
valid_sources[0x1e]	7678	1			T7	2		T44	5		T9	21
valid_sources[0x1f]	6959	1			T5	1		T6	1		T2	1
valid_sources[0x20]	12386	1			T1	7		T2	6		T27	1
valid_sources[0x21]	6781	1			T1	2		T2	3		T30	1
valid_sources[0x22]	6903	1			T5	2		T1	4		T2	3
valid_sources[0x23]	8169	1			T5	1		T1	4		T24	1
valid_sources[0x24]	6692	1			T1	3		T2	1		T7	1
valid_sources[0x25]	6769	1			T1	6		T30	1		T7	7
valid_sources[0x26]	20115	1			T5	2		T2	4		T7	1
valid_sources[0x27]	6586	1			T5	2		T1	1		T2	1
valid_sources[0x28]	7198	1			T1	2		T2	2		T4	1
valid_sources[0x29]	6654	1			T5	1		T1	4		T6	3
valid_sources[0x2a]	8270	1			T5	1		T1	4		T2	4
valid_sources[0x2b]	19925	1			T1	2		T2	6		T7	2
valid_sources[0x2c]	6960	1			T5	1		T1	4		T6	7
valid_sources[0x2d]	7400	1			T1	1		T2	1		T4	1
valid_sources[0x2e]	6495	1			T1	2		T24	1		T4	1
valid_sources[0x2f]	6532	1			T1	4		T6	10		T2	2
valid_sources[0x30]	7242	1			T5	1		T1	2		T2	3
valid_sources[0x31]	7437	1			T5	2		T1	1		T2	3
valid_sources[0x32]	8370	1			T5	5		T1	1		T2	3
valid_sources[0x33]	6794	1			T1	6		T4	2		T7	2
valid_sources[0x34]	9598	1			T5	2		T1	6		T2	1
valid_sources[0x35]	7327	1			T5	2		T1	5		T2	2
valid_sources[0x36]	6688	1			T26	1		T30	1		T9	20
valid_sources[0x37]	8233	1			T5	2		T1	6		T2	4
valid_sources[0x38]	6838	1			T1	1		T26	1		T44	1
valid_sources[0x39]	7748	1			T5	1		T1	5		T2	4
valid_sources[0x3a]	8494	1			T5	3		T1	7		T2	8
valid_sources[0x3b]	13698	1			T5	1		T1	1		T2	12
valid_sources[0x3c]	6945	1			T5	1		T2	2		T4	1
valid_sources[0x3d]	6674	1			T1	3		T2	2		T7	2
valid_sources[0x3e]	7191	1			T2	3		T7	3		T44	3
valid_sources[0x3f]	7529	1			T1	8		T2	1		T4	1
valid_sources[0x40]	10744	1			T5	1		T2	5		T26	1
valid_sources[0x41]	6984	1			T5	1		T1	4		T2	5
valid_sources[0x42]	16850	1			T1	4		T2	4		T7	1
valid_sources[0x43]	6315	1			T5	2		T1	4		T7	3
valid_sources[0x44]	6757	1			T1	4		T2	4		T4	2
valid_sources[0x45]	11015	1			T5	1		T1	2		T2	2
valid_sources[0x46]	6874	1			T5	1		T1	1		T4	1
valid_sources[0x47]	7439	1			T1	3		T24	1		T2	2
valid_sources[0x48]	8522	1			T5	2		T1	1		T2	3
valid_sources[0x49]	6534	1			T1	3		T2	6		T44	8
valid_sources[0x4a]	7749	1			T1	3		T2	8		T7	3
valid_sources[0x4b]	7130	1			T1	2		T2	1		T44	7
valid_sources[0x4c]	9427	1			T5	1		T1	3		T2	11
valid_sources[0x4d]	7310	1			T5	3		T1	2		T2	6
valid_sources[0x4e]	11503	1			T5	1		T1	6		T2	5
valid_sources[0x4f]	6596	1			T1	2		T3	17		T25	14
valid_sources[0x50]	15411	1			T1	2		T4	1		T7	2
valid_sources[0x51]	7105	1			T5	2		T1	10		T2	6
valid_sources[0x52]	6804	1			T7	2		T44	3		T9	19
valid_sources[0x53]	8090	1			T1	4		T2	11		T4	2
valid_sources[0x54]	6664	1			T1	4		T2	2		T7	1
valid_sources[0x55]	7248	1			T1	5		T2	4		T27	1
valid_sources[0x56]	11560	1			T1	3		T2	11		T32	3
valid_sources[0x57]	14757	1			T5	2		T1	5		T6	11
valid_sources[0x58]	12189	1			T5	2		T1	7		T2	12
valid_sources[0x59]	6898	1			T5	2		T1	3		T2	5
valid_sources[0x5a]	11372	1			T5	1		T1	8		T2	5
valid_sources[0x5b]	11658	1			T1	1		T2	3		T7	2
valid_sources[0x5c]	14202	1			T1	6		T2	3		T7	2
valid_sources[0x5d]	6942	1			T5	1		T1	1		T2	4
valid_sources[0x5e]	15277	1			T1	6		T2	3		T4	1
valid_sources[0x5f]	19814	1			T2	4		T26	1		T27	1
valid_sources[0x60]	6847	1			T1	2		T2	2		T4	1
valid_sources[0x61]	8913	1			T1	1		T2	9		T7	3
valid_sources[0x62]	6620	1			T1	7		T2	3		T7	1
valid_sources[0x63]	7996	1			T1	5		T2	4		T9	34
valid_sources[0x64]	6767	1			T5	2		T2	13		T7	2
valid_sources[0x65]	9401	1			T5	2		T1	1		T2	7
valid_sources[0x66]	6833	1			T5	2		T1	2		T2	1
valid_sources[0x67]	15475	1			T1	4		T2	5		T7	2
valid_sources[0x68]	7206	1			T1	1		T2	5		T4	1
valid_sources[0x69]	11366	1			T3	4		T26	1		T44	4
valid_sources[0x6a]	11340	1			T1	1		T2	6		T27	1
valid_sources[0x6b]	7724	1			T1	3		T2	5		T4	2
valid_sources[0x6c]	7847	1			T1	3		T2	4		T7	1
valid_sources[0x6d]	6658	1			T5	2		T1	4		T2	8
valid_sources[0x6e]	6686	1			T1	4		T2	1		T27	2
valid_sources[0x6f]	8329	1			T5	2		T1	4		T2	6
valid_sources[0x70]	8078	1			T1	2		T2	2		T4	3
valid_sources[0x71]	12062	1			T5	1		T1	3		T2	1
valid_sources[0x72]	11313	1			T1	5		T2	2		T4	1
valid_sources[0x73]	6772	1			T5	3		T2	5		T4	1
valid_sources[0x74]	10785	1			T1	3		T4	1		T7	2
valid_sources[0x75]	7376	1			T5	1		T1	11		T2	5
valid_sources[0x76]	6979	1			T1	2		T2	5		T4	1
valid_sources[0x77]	8262	1			T1	1		T2	1		T26	2
valid_sources[0x78]	7000	1			T5	1		T1	3		T7	2
valid_sources[0x79]	10748	1			T5	1		T1	1		T2	2
valid_sources[0x7a]	7474	1			T5	4		T1	3		T2	5
valid_sources[0x7b]	6490	1			T5	2		T1	4		T2	4
valid_sources[0x7c]	6516	1			T5	1		T1	4		T2	2
valid_sources[0x7d]	9393	1			T5	2		T1	4		T44	5
valid_sources[0x7e]	9483	1			T1	10		T2	1		T4	1
valid_sources[0x7f]	6889	1			T1	4		T2	2		T26	1
valid_sources[0x80]	6998	1			T1	3		T2	6		T25	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049357

1

T5

46

T1

58

T6

8

values[0x0]

all_enables

biggest_size

71613

1

T5

63

T1

103

T6

3

values[0x1]

all_enables

biggest_size

51253

1

T5

66

T1

122

T6

4