Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28927	1			T1	2		T3	9		T7	207
auto[PWRUP]	123	1			T41	3		T42	1		T43	1
auto[ONEST_0]	48	1			T41	1		T189	2		T190	1
auto[ONEST_021]	14	1			T41	1		T42	2		T189	1
auto[ONEST_1]	73	1			T42	1		T189	1		T190	1
auto[ONEST_DONE]	9	1			T191	1		T192	1		T193	1
auto[LP_0]	131	1			T22	1		T41	2		T42	2
auto[LP_021]	19	1			T190	1		T194	1		T195	1
auto[LP_1]	101	1			T42	1		T189	5		T194	1
auto[LP_EVAL]	69	1			T41	2		T42	1		T43	1
auto[LP_SLP]	482	1			T22	1		T41	4		T42	3
auto[LP_PWRUP]	25	1			T41	1		T189	1		T196	1
auto[NP_0]	162	1			T41	1		T43	1		T190	4
auto[NP_021]	33	1			T41	1		T189	1		T194	2
auto[NP_1]	144	1			T41	5		T42	2		T189	3
auto[NP_EVAL]	44	1			T189	1		T190	1		T85	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T59

1

T164

1

T197

1

min

28429

1

T1

2

T3

9

T7

207

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28434	1			T1	2		T3	9		T7	207
pow[0x1]	9	1			T189	1		T85	1		T198	1
pow[0x2]	16	1			T194	1		T85	1		T199	1
pow[0x3]	27	1			T194	1		T85	1		T200	2
pow[0x4]	51	1			T41	2		T190	1		T194	2
pow[0x5]	124	1			T41	1		T42	2		T43	1
pow[0x6]	243	1			T41	4		T42	5		T189	1
pow[0x7]	524	1			T41	11		T42	4		T43	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

183

1

T41

3

T42

1

T43

1

min

27993

1

T1

2

T3

9

T7

207

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27993	1			T1	2		T3	9		T7	207
pow[0x5]	2	1			T200	1		T201	1		-	-
pow[0x6]	3	1			T202	1		T203	1		T204	1
pow[0x7]	4	1			T42	1		T59	1		T191	1
pow[0x8]	7	1			T41	1		T141	1		T191	1
pow[0x9]	7	1			T141	1		T59	1		T205	1
pow[0xa]	20	1			T41	1		T194	1		T200	1
pow[0xb]	31	1			T190	1		T85	1		T59	1
pow[0xc]	69	1			T189	1		T190	1		T194	1
pow[0xd]	138	1			T41	2		T42	1		T43	1
pow[0xe]	274	1			T22	1		T41	6		T42	3
pow[0xf]	582	1			T41	13		T42	6		T43	1