Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2288	1			T1	10		T25	2		T30	1
auto[PWRUP]	146	1			T22	1		T42	1		T189	1
auto[ONEST_0]	68	1			T189	1		T190	1		T194	1
auto[ONEST_021]	20	1			T20	1		T115	1		T198	1
auto[ONEST_1]	72	1			T41	2		T190	2		T194	1
auto[ONEST_DONE]	4	1			T361	1		T362	1		T363	1
auto[LP_0]	113	1			T41	2		T42	2		T189	2
auto[LP_021]	25	1			T41	2		T189	1		T115	2
auto[LP_1]	119	1			T41	1		T42	1		T189	4
auto[LP_EVAL]	48	1			T41	2		T42	1		T194	1
auto[LP_SLP]	519	1			T22	1		T41	5		T42	6
auto[LP_PWRUP]	24	1			T42	1		T189	2		T194	2
auto[NP_0]	236	1			T20	4		T41	3		T42	3
auto[NP_021]	56	1			T43	1		T38	1		T194	2
auto[NP_1]	205	1			T22	4		T43	2		T38	3
auto[NP_EVAL]	27	1			T189	1		T115	1		T118	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T85

1

T192

1

T212

1

min

1929

1

T1

10

T25

2

T30

1

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1943	1			T1	10		T25	2		T30	1
pow[0x1]	6	1			T155	1		T364	1		T365	1
pow[0x2]	14	1			T189	1		T366	1		T248	1
pow[0x3]	37	1			T41	1		T42	1		T194	1
pow[0x4]	59	1			T41	1		T42	1		T190	1
pow[0x5]	122	1			T41	1		T42	1		T189	4
pow[0x6]	251	1			T22	1		T41	2		T42	2
pow[0x7]	525	1			T41	9		T42	9		T189	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T41

2

T42

2

T43

1

min

1387

1

T1

10

T25

2

T30

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1392	1			T1	10		T25	2		T30	1
pow[0x1]	16	1			T38	1		T118	7		T59	1
pow[0x2]	20	1			T20	4		T38	1		T317	1
pow[0x3]	39	1			T22	1		T38	1		T155	2
pow[0x4]	65	1			T22	1		T38	3		T59	1
pow[0x5]	2	1			T367	1		T361	1		-	-
pow[0x6]	2	1			T368	1		T369	1		-	-
pow[0x7]	3	1			T370	1		T371	1		T264	1
pow[0x8]	7	1			T56	1		T372	1		T373	1
pow[0x9]	15	1			T42	1		T374	1		T375	1
pow[0xa]	20	1			T194	1		T200	1		T55	1
pow[0xb]	41	1			T189	3		T190	1		T194	1
pow[0xc]	73	1			T42	2		T189	2		T194	2
pow[0xd]	114	1			T41	2		T42	3		T189	1
pow[0xe]	276	1			T41	3		T42	4		T189	5
pow[0xf]	555	1			T22	1		T41	8		T42	8