Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T11,T12,T17

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T10,T11,T13

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T18
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T14,T17,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T18
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T18
0	1	Covered	T13,T17,T18
1	0	Covered	T13,T17,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T22
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T23
0	1	Covered	T14,T17,T23
1	0	Covered	T14,T17,T22

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T18
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T14,T17,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T17,T18,T20
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T17,T18,T20
1	0	Covered	T17,T18,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T15
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T11,T12,T13
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T13,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T17,T18,T20
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T22
0	1	Covered	T17,T18,T89
1	0	Covered	T17,T18,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T22
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T23
0	1	Covered	T14,T17,T23
1	0	Covered	T14,T17,T22

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T18
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T14,T17,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T17,T18,T20
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T17,T18,T23
1	0	Covered	T17,T18,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T15
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T11,T12,T13
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T15
1	1	0	Covered	T10,T13,T15
1	1	1	Covered	T10,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T14
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T14
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T14,T15
1	1	0	Covered	T10,T14,T15
1	1	1	Covered	T10,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T15
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T15
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T14,T15
1	1	0	Covered	T10,T15,T17
1	1	1	Covered	T10,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T15
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T15,T17

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T14
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T14
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T15
1	1	0	Covered	T10,T13,T15
1	1	1	Covered	T10,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T17
0	1	Covered	T10,T11,T13
0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T14,T17,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T17,T18,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T14,T17,T22

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T14,T17,T22

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T14,T17,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T14,T17,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T17,T18,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T17,T18,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32330952	32025874	0	0
gen_filter_match[0].MatchCheck00_A	32330952	9917119	0	0
gen_filter_match[0].MatchCheck01_A	32330952	2183261	0	0
gen_filter_match[0].MatchCheck10_A	32330952	2306627	0	0
gen_filter_match[0].MatchCheck11_A	32330952	17618867	0	0
gen_filter_match[1].MatchCheck00_A	32330952	10160055	0	0
gen_filter_match[1].MatchCheck01_A	32330952	1097682	0	0
gen_filter_match[1].MatchCheck10_A	32330952	1349949	0	0
gen_filter_match[1].MatchCheck11_A	32330952	19418188	0	0
gen_filter_match[2].MatchCheck00_A	32330952	11156282	0	0
gen_filter_match[2].MatchCheck01_A	32330952	550567	0	0
gen_filter_match[2].MatchCheck10_A	32330952	563009	0	0
gen_filter_match[2].MatchCheck11_A	32330952	19756016	0	0
gen_filter_match[3].MatchCheck00_A	32330952	11442067	0	0
gen_filter_match[3].MatchCheck01_A	32330952	294981	0	0
gen_filter_match[3].MatchCheck10_A	32330952	318864	0	0
gen_filter_match[3].MatchCheck11_A	32330952	19969962	0	0
gen_filter_match[4].MatchCheck00_A	32330952	11712699	0	0
gen_filter_match[4].MatchCheck01_A	32330952	83915	0	0
gen_filter_match[4].MatchCheck10_A	32330952	67614	0	0
gen_filter_match[4].MatchCheck11_A	32330952	20161646	0	0
gen_filter_match[5].MatchCheck00_A	32330952	12257490	0	0
gen_filter_match[5].MatchCheck01_A	32330952	10	0	0
gen_filter_match[5].MatchCheck10_A	32330952	99	0	0
gen_filter_match[5].MatchCheck11_A	32330952	19768275	0	0
gen_filter_match[6].MatchCheck00_A	32330952	11885198	0	0
gen_filter_match[6].MatchCheck01_A	32330952	32878	0	0
gen_filter_match[6].MatchCheck10_A	32330952	119	0	0
gen_filter_match[6].MatchCheck11_A	32330952	20107679	0	0
gen_filter_match[7].MatchCheck00_A	32330952	12566820	0	0
gen_filter_match[7].MatchCheck01_A	32330952	235032	0	0
gen_filter_match[7].MatchCheck10_A	32330952	130393	0	0
gen_filter_match[7].MatchCheck11_A	32330952	19093629	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	32025874	0	0
T10	65856	65783	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	66177	0	0
T14	67503	67447	0	0
T15	34158	34059	0	0
T16	4588	4496	0	0
T17	98625	98248	0	0
T18	99623	99533	0	0
T19	5208	5150	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	9917119	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	33921	0	0
T14	67503	67447	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	748	0	0
T18	99623	33693	0	0
T19	5208	5150	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	2183261	0	0
T18	99623	65840	0	0
T19	5208	0	0	0
T20	20901	0	0	0
T21	66329	0	0	0
T22	7225	0	0	0
T23	33270	0	0	0
T39	0	32801	0	0
T41	19884	0	0	0
T62	63960	32768	0	0
T63	32179	0	0	0
T86	1155	0	0	0
T90	0	31838	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	33269	0	0
T94	0	31733	0	0
T95	0	1	0	0
T96	0	33708	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	2306627	0	0
T17	98625	32338	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T20	20901	0	0	0
T21	66329	0	0	0
T22	7225	0	0	0
T23	33270	33192	0	0
T41	19884	0	0	0
T62	63960	31096	0	0
T86	1155	0	0	0
T90	0	32695	0	0
T91	0	2	0	0
T92	0	3	0	0
T97	0	31906	0	0
T98	0	33166	0	0
T99	0	32096	0	0
T100	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	17618867	0	0
T10	65856	65779	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	32256	0	0
T14	67503	0	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	65162	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T21	0	66269	0	0
T22	0	121	0	0
T41	0	639	0	0
T89	0	64438	0	0
T101	0	32756	0	0
T102	0	65521	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	10160055	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	3	0	0
T14	67503	34820	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	33086	0	0
T18	99623	33693	0	0
T19	5208	5150	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	1097682	0	0
T95	97261	0	0	0
T103	98456	32200	0	0
T104	98682	65856	0	0
T105	0	32637	0	0
T106	0	33540	0	0
T107	0	32765	0	0
T108	0	33738	0	0
T109	0	31467	0	0
T110	0	32333	0	0
T111	0	12916	0	0
T112	0	32534	0	0
T113	819	0	0	0
T114	34518	0	0	0
T115	13471	0	0	0
T116	97267	0	0	0
T117	32335	0	0	0
T118	57372	0	0	0
T119	33375	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	1349949	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	33127	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T89	0	32029	0	0
T91	0	2	0	0
T92	0	32801	0	0
T100	0	32640	0	0
T103	0	32496	0	0
T120	0	34462	0	0
T121	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	19418188	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	66174	0	0
T14	67503	32626	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	32035	0	0
T18	99623	65840	0	0
T19	5208	0	0	0
T20	0	20122	0	0
T21	0	66269	0	0
T101	0	32756	0	0
T102	0	64752	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	11156282	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	3	0	0
T14	67503	32630	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	33086	0	0
T18	99623	32511	0	0
T19	5208	5150	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	550567	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T20	20901	0	0	0
T21	66329	0	0	0
T22	7225	0	0	0
T38	0	24209	0	0
T86	1155	0	0	0
T95	0	32319	0	0
T122	0	33643	0	0
T123	0	1	0	0
T124	0	32836	0	0
T125	0	32569	0	0
T126	0	1	0	0
T127	0	33067	0	0
T128	0	1	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	563009	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T23	0	1	0	0
T92	0	3	0	0
T95	0	2	0	0
T100	0	1	0	0
T102	0	32788	0	0
T121	0	1	0	0
T129	0	1	0	0
T130	0	32942	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	19756016	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	66174	0	0
T14	67503	34815	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	65162	0	0
T18	99623	67022	0	0
T19	5208	0	0	0
T21	0	66269	0	0
T22	0	4973	0	0
T23	0	33191	0	0
T62	0	32768	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	11442067	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	66177	0	0
T14	67503	34820	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	748	0	0
T18	99623	33335	0	0
T19	5208	5150	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	294981	0	0
T93	97958	32533	0	0
T94	65414	0	0	0
T95	0	2	0	0
T96	0	32583	0	0
T104	98682	1	0	0
T125	0	31998	0	0
T130	64537	0	0	0
T131	0	1	0	0
T132	0	33093	0	0
T133	0	1	0	0
T134	0	31700	0	0
T135	0	31753	0	0
T136	1111	0	0	0
T137	97254	0	0	0
T138	65505	0	0	0
T139	32712	0	0	0
T140	6233	0	0	0
T141	17947	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	318864	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T23	0	2	0	0
T58	0	1	0	0
T92	0	3	0	0
T95	0	2	0	0
T100	0	1	0	0
T118	0	6	0	0
T121	0	1	0	0
T142	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	19969962	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	32626	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	97500	0	0
T18	99623	66198	0	0
T19	5208	0	0	0
T21	0	66269	0	0
T22	0	4973	0	0
T23	0	33190	0	0
T62	0	32768	0	0
T89	0	64438	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	11712699	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	66177	0	0
T14	67503	32631	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	65121	0	0
T18	99623	67025	0	0
T19	5208	5150	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	83915	0	0
T39	66658	0	0	0
T92	65129	2	0	0
T95	0	2	0	0
T97	64789	0	0	0
T104	98682	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	83903	0	0
T149	5148	0	0	0
T150	33164	0	0	0
T151	33750	0	0	0
T152	5232	0	0	0
T153	729	0	0	0
T154	9433	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	67614	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	34816	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T92	0	3	0	0
T95	0	2	0	0
T100	0	1	0	0
T104	0	1	0	0
T118	0	7	0	0
T121	0	1	0	0
T129	0	1	0	0
T155	0	3	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	20161646	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	0	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	33127	0	0
T18	99623	32508	0	0
T19	5208	0	0	0
T20	0	20122	0	0
T21	0	66269	0	0
T63	0	32085	0	0
T89	0	64438	0	0
T101	0	32756	0	0
T102	0	65521	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	12257490	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	32259	0	0
T14	67503	4	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	65910	0	0
T18	99623	33693	0	0
T19	5208	5150	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	10	0	0
T126	99975	1	0	0
T127	65557	0	0	0
T134	73584	0	0	0
T146	0	1	0	0
T156	64937	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	66	0	0	0
T163	4747	0	0	0
T164	17658	0	0	0
T165	1117	0	0	0
T166	66702	0	0	0
T167	7900	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	99	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T91	0	2	0	0
T104	0	1	0	0
T118	0	7	0	0
T121	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	19768275	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	33918	0	0
T14	67503	67442	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	32338	0	0
T18	99623	65840	0	0
T19	5208	0	0	0
T20	0	20122	0	0
T21	0	66269	0	0
T22	0	4973	0	0
T62	0	63864	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	11885198	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	33921	0	0
T14	67503	34820	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	65121	0	0
T18	99623	32511	0	0
T19	5208	5150	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	32878	0	0
T39	66658	0	0	0
T92	65129	2	0	0
T97	64789	0	0	0
T104	98682	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T133	0	1	0	0
T134	0	32864	0	0
T144	0	1	0	0
T149	5148	0	0	0
T150	33164	0	0	0
T151	33750	0	0	0
T152	5232	0	0	0
T153	729	0	0	0
T154	9433	0	0	0
T157	0	1	0	0
T158	0	2	0	0
T170	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	119	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	1	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T23	0	1	0	0
T92	0	3	0	0
T95	0	2	0	0
T100	0	1	0	0
T104	0	2	0	0
T114	0	1	0	0
T121	0	1	0	0
T129	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	20107679	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	32256	0	0
T14	67503	32626	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	33127	0	0
T18	99623	67022	0	0
T19	5208	0	0	0
T21	0	66269	0	0
T22	0	4973	0	0
T23	0	33190	0	0
T89	0	32029	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	12566820	0	0
T10	65856	4	0	0
T11	834	772	0	0
T12	1141	1058	0	0
T13	66251	32259	0	0
T14	67503	67447	0	0
T15	34158	4	0	0
T16	4588	4496	0	0
T17	98625	65910	0	0
T18	99623	65843	0	0
T19	5208	5150	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	235032	0	0
T38	39161	0	0	0
T42	15889	0	0	0
T43	4903	0	0	0
T45	56	0	0	0
T46	59	0	0	0
T90	64587	0	0	0
T91	66003	0	0	0
T102	97629	32733	0	0
T104	0	1	0	0
T123	0	1	0	0
T131	0	1	0	0
T171	0	32731	0	0
T172	0	2	0	0
T173	0	32302	0	0
T174	0	38387	0	0
T175	0	33293	0	0
T176	0	32038	0	0
T177	5030	0	0	0
T178	6683	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	130393	0	0
T10	65856	1	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	0	0	0
T14	67503	0	0	0
T15	34158	0	0	0
T16	4588	0	0	0
T17	98625	0	0	0
T18	99623	0	0	0
T19	5208	0	0	0
T23	0	1	0	0
T91	0	2	0	0
T92	0	3	0	0
T95	0	1	0	0
T100	0	1	0	0
T104	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0
T121	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32330952	19093629	0	0
T10	65856	65778	0	0
T11	834	0	0	0
T12	1141	0	0	0
T13	66251	33918	0	0
T14	67503	0	0	0
T15	34158	34055	0	0
T16	4588	0	0	0
T17	98625	32338	0	0
T18	99623	33690	0	0
T19	5208	0	0	0
T20	0	20122	0	0
T21	0	66269	0	0
T23	0	33190	0	0
T62	0	63864	0	0
T102	0	64807	0	0