Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6441	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1160	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1329	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1176	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1239	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1281	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1262	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1111	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1254	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1119	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1147	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1246	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1256	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1182	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1177	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1260	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1303	0	0
adc_en_ctl_rd_A	2147483647	941	0	0
adc_fsm_rst_rd_A	2147483647	899	0	0
adc_intr_ctl_rd_A	2147483647	815	0	0
adc_lp_sample_ctl_rd_A	2147483647	787	0	0
adc_pd_ctl_rd_A	2147483647	1140	0	0
adc_sample_ctl_rd_A	2147483647	789	0	0
adc_wakeup_ctl_rd_A	2147483647	834	0	0
intr_enable_rd_A	2147483647	1159	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6441	0	0
T1	210731	0	0	0
T2	82465	0	0	0
T3	45573	0	0	0
T4	9220	0	0	0
T5	7428	127	0	0
T6	13695	0	0	0
T24	31881	0	0	0
T25	45224	0	0	0
T26	48843	366	0	0
T27	10417	0	0	0
T30	0	1	0	0
T44	0	570	0	0
T64	0	551	0	0
T65	0	271	0	0
T66	0	1	0	0
T67	0	201	0	0
T68	0	197	0	0
T69	0	858	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1160	0	0
T8	13493	20	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	72	0	0
T34	21489	0	0	0
T35	76180	12	0	0
T40	108533	0	0	0
T65	0	8	0	0
T68	0	5	0	0
T78	0	17	0	0
T84	0	26	0	0
T179	0	73	0	0
T180	0	6	0	0
T181	0	33	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T8	13493	4	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	30	0	0
T34	21489	0	0	0
T35	76180	23	0	0
T40	108533	0	0	0
T65	0	28	0	0
T68	0	17	0	0
T70	0	30	0	0
T84	0	14	0	0
T179	0	141	0	0
T180	0	11	0	0
T181	0	48	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1176	0	0
T7	105983	0	0	0
T8	13493	3	0	0
T9	461483	0	0	0
T30	10308	9	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	31	0	0
T35	0	24	0	0
T44	48476	0	0	0
T65	0	4	0	0
T68	0	6	0	0
T82	52642	0	0	0
T84	0	6	0	0
T179	0	123	0	0
T180	0	15	0	0
T181	0	72	0	0
T182	10203	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1239	0	0
T8	13493	8	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	54	0	0
T34	21489	0	0	0
T35	76180	27	0	0
T40	108533	0	0	0
T65	0	12	0	0
T68	0	17	0	0
T78	0	13	0	0
T84	0	18	0	0
T179	0	89	0	0
T180	0	13	0	0
T181	0	34	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281	0	0
T7	105983	0	0	0
T8	13493	8	0	0
T9	461483	0	0	0
T30	10308	7	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	52	0	0
T35	0	59	0	0
T44	48476	0	0	0
T68	0	29	0	0
T78	0	26	0	0
T82	52642	0	0	0
T84	0	24	0	0
T179	0	120	0	0
T180	0	15	0	0
T181	0	19	0	0
T182	10203	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1262	0	0
T8	13493	7	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	60	0	0
T34	21489	0	0	0
T35	76180	15	0	0
T40	108533	0	0	0
T65	0	7	0	0
T68	0	14	0	0
T70	0	3	0	0
T84	0	4	0	0
T179	0	98	0	0
T180	0	19	0	0
T181	0	65	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1111	0	0
T7	105983	0	0	0
T8	13493	5	0	0
T9	461483	0	0	0
T30	10308	3	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	73	0	0
T35	0	11	0	0
T44	48476	0	0	0
T65	0	8	0	0
T68	0	6	0	0
T82	52642	0	0	0
T84	0	22	0	0
T179	0	79	0	0
T180	0	6	0	0
T181	0	38	0	0
T182	10203	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1254	0	0
T7	105983	0	0	0
T8	13493	11	0	0
T9	461483	0	0	0
T30	10308	8	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	28	0	0
T35	0	8	0	0
T44	48476	0	0	0
T65	0	10	0	0
T68	0	7	0	0
T82	52642	0	0	0
T84	0	12	0	0
T179	0	120	0	0
T180	0	49	0	0
T181	0	33	0	0
T182	10203	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1119	0	0
T7	105983	0	0	0
T8	13493	14	0	0
T9	461483	0	0	0
T30	10308	6	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	43	0	0
T35	0	32	0	0
T44	48476	0	0	0
T65	0	2	0	0
T68	0	10	0	0
T70	0	4	0	0
T82	52642	0	0	0
T84	0	24	0	0
T179	0	85	0	0
T180	0	24	0	0
T182	10203	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T7	105983	0	0	0
T8	13493	1	0	0
T9	461483	0	0	0
T30	10308	7	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	69	0	0
T35	0	7	0	0
T44	48476	0	0	0
T65	0	13	0	0
T68	0	12	0	0
T70	0	9	0	0
T82	52642	0	0	0
T84	0	19	0	0
T179	0	72	0	0
T180	0	5	0	0
T182	10203	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1246	0	0
T8	13493	8	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	46	0	0
T34	21489	0	0	0
T35	76180	35	0	0
T40	108533	0	0	0
T65	0	27	0	0
T70	0	5	0	0
T78	0	32	0	0
T84	0	22	0	0
T179	0	120	0	0
T180	0	28	0	0
T181	0	61	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256	0	0
T7	105983	0	0	0
T8	13493	16	0	0
T9	461483	0	0	0
T30	10308	2	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	57	0	0
T35	0	32	0	0
T44	48476	0	0	0
T65	0	16	0	0
T68	0	3	0	0
T70	0	6	0	0
T82	52642	0	0	0
T84	0	37	0	0
T179	0	104	0	0
T180	0	25	0	0
T182	10203	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1182	0	0
T8	13493	6	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	48	0	0
T34	21489	0	0	0
T35	76180	12	0	0
T40	108533	0	0	0
T78	0	19	0	0
T84	0	28	0	0
T179	0	60	0	0
T180	0	25	0	0
T181	0	42	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0
T185	0	8	0	0
T186	0	8	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1177	0	0
T8	13493	22	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	35	0	0
T34	21489	0	0	0
T35	76180	28	0	0
T40	108533	0	0	0
T65	0	17	0	0
T68	0	8	0	0
T70	0	2	0	0
T84	0	14	0	0
T179	0	101	0	0
T180	0	51	0	0
T181	0	44	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1260	0	0
T29	890321	0	0	0
T33	102432	32	0	0
T34	21489	0	0	0
T35	76180	18	0	0
T36	86582	0	0	0
T40	108533	0	0	0
T64	37568	0	0	0
T65	0	10	0	0
T68	0	1	0	0
T78	0	20	0	0
T84	0	20	0	0
T179	0	102	0	0
T180	0	26	0	0
T181	0	21	0	0
T183	3284	0	0	0
T184	38246	0	0	0
T185	0	9	0	0
T187	33542	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T8	13493	3	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	40	0	0
T34	21489	0	0	0
T35	76180	22	0	0
T40	108533	0	0	0
T65	0	10	0	0
T68	0	2	0	0
T70	0	8	0	0
T84	0	22	0	0
T179	0	66	0	0
T180	0	20	0	0
T181	0	15	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	941	0	0
T29	890321	0	0	0
T33	102432	31	0	0
T34	21489	0	0	0
T35	76180	22	0	0
T36	86582	0	0	0
T40	108533	0	0	0
T64	37568	0	0	0
T65	0	1	0	0
T70	0	2	0	0
T78	0	5	0	0
T84	0	11	0	0
T179	0	64	0	0
T180	0	10	0	0
T181	0	30	0	0
T183	3284	0	0	0
T184	38246	0	0	0
T185	0	16	0	0
T187	33542	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	899	0	0
T8	13493	5	0	0
T9	461483	0	0	0
T29	890321	0	0	0
T33	102432	21	0	0
T34	21489	0	0	0
T35	76180	30	0	0
T40	108533	0	0	0
T65	0	21	0	0
T68	0	5	0	0
T70	0	12	0	0
T84	0	8	0	0
T179	0	53	0	0
T180	0	28	0	0
T181	0	59	0	0
T182	10203	0	0	0
T183	3284	0	0	0
T184	38246	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	815	0	0
T29	890321	0	0	0
T33	102432	26	0	0
T34	21489	0	0	0
T35	76180	8	0	0
T36	86582	0	0	0
T40	108533	0	0	0
T64	37568	0	0	0
T65	0	11	0	0
T68	0	6	0	0
T84	0	10	0	0
T179	0	41	0	0
T180	0	4	0	0
T181	0	5	0	0
T183	3284	0	0	0
T184	38246	0	0	0
T185	0	15	0	0
T186	0	7	0	0
T187	33542	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	787	0	0
T7	105983	0	0	0
T8	13493	4	0	0
T9	461483	0	0	0
T30	10308	6	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	11	0	0
T35	0	28	0	0
T44	48476	0	0	0
T65	0	11	0	0
T68	0	8	0	0
T70	0	3	0	0
T82	52642	0	0	0
T84	0	2	0	0
T179	0	37	0	0
T180	0	6	0	0
T182	10203	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1140	0	0
T29	890321	0	0	0
T33	102432	41	0	0
T34	21489	0	0	0
T35	76180	9	0	0
T36	86582	0	0	0
T40	108533	0	0	0
T64	37568	0	0	0
T65	0	9	0	0
T68	0	5	0	0
T70	0	9	0	0
T78	0	11	0	0
T84	0	20	0	0
T179	0	108	0	0
T180	0	20	0	0
T181	0	26	0	0
T183	3284	0	0	0
T184	38246	0	0	0
T187	33542	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	789	0	0
T7	105983	0	0	0
T8	13493	5	0	0
T9	461483	0	0	0
T30	10308	1	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	27	0	0
T35	0	16	0	0
T44	48476	0	0	0
T65	0	7	0	0
T68	0	5	0	0
T70	0	3	0	0
T82	52642	0	0	0
T84	0	7	0	0
T179	0	41	0	0
T180	0	15	0	0
T182	10203	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	834	0	0
T7	105983	0	0	0
T8	13493	5	0	0
T9	461483	0	0	0
T30	10308	7	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	102432	25	0	0
T35	0	26	0	0
T44	48476	0	0	0
T65	0	11	0	0
T68	0	17	0	0
T70	0	24	0	0
T82	52642	0	0	0
T84	0	6	0	0
T179	0	35	0	0
T180	0	11	0	0
T182	10203	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T7	105983	0	0	0
T8	13493	8	0	0
T9	461483	0	0	0
T28	21268	21	0	0
T30	10308	7	0	0
T31	35502	0	0	0
T32	19443	0	0	0
T33	0	30	0	0
T35	0	4	0	0
T44	48476	0	0	0
T65	0	13	0	0
T68	0	3	0	0
T82	52642	11	0	0
T182	10203	0	0	0
T183	0	19	0	0
T188	0	8	0	0