Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1166358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1122157

1

T5

15

T1

300

T6

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1999755	1			T5	19		T1	565		T6	20
values[0x0]	143775	1			T5	10		T1	129		T6	9
values[0x1]	144985	1			T5	11		T1	159		T6	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	939123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1349392

1

T5

17

T1

509

T6

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7498	1			T25	1		T4	8		T41	2
valid_sources[0x01]	19293	1			T1	9		T4	6		T30	3
valid_sources[0x02]	7219	1			T2	46		T3	1		T25	1
valid_sources[0x03]	6899	1			T4	7		T11	2		T30	3
valid_sources[0x04]	13620	1			T6	3		T3	1		T4	9
valid_sources[0x05]	6873	1			T2	1		T3	6		T4	3
valid_sources[0x06]	6857	1			T3	8		T4	5		T26	5
valid_sources[0x07]	7200	1			T1	25		T3	1		T4	7
valid_sources[0x08]	10927	1			T3	4		T4	3		T8	3
valid_sources[0x09]	6784	1			T6	2		T25	1		T4	8
valid_sources[0x0a]	11138	1			T3	3		T4	7		T10	2
valid_sources[0x0b]	6362	1			T4	12		T11	3		T30	3
valid_sources[0x0c]	8835	1			T2	1		T3	6		T4	8
valid_sources[0x0d]	11256	1			T3	3		T4	7		T26	3
valid_sources[0x0e]	6875	1			T1	14		T4	8		T8	11
valid_sources[0x0f]	7023	1			T4	4		T63	2		T30	11
valid_sources[0x10]	7210	1			T1	7		T2	14		T3	4
valid_sources[0x11]	6520	1			T2	1		T3	2		T4	8
valid_sources[0x12]	6705	1			T3	5		T4	7		T10	1
valid_sources[0x13]	7112	1			T1	5		T2	15		T3	2
valid_sources[0x14]	6486	1			T1	14		T3	6		T4	5
valid_sources[0x15]	6759	1			T6	1		T3	1		T4	4
valid_sources[0x16]	6869	1			T1	14		T3	8		T4	5
valid_sources[0x17]	6856	1			T2	150		T3	1		T4	7
valid_sources[0x18]	7377	1			T4	3		T30	4		T31	3
valid_sources[0x19]	6432	1			T2	60		T4	2		T10	2
valid_sources[0x1a]	14548	1			T3	1		T4	8		T26	5
valid_sources[0x1b]	12967	1			T3	7		T4	5		T8	5
valid_sources[0x1c]	8458	1			T3	1		T4	2		T10	3
valid_sources[0x1d]	8022	1			T2	42		T3	6		T4	11
valid_sources[0x1e]	11169	1			T1	1		T2	71		T3	3
valid_sources[0x1f]	11247	1			T3	16		T25	2		T4	3
valid_sources[0x20]	8527	1			T3	4		T25	1		T4	5
valid_sources[0x21]	13843	1			T2	88		T25	4		T4	3
valid_sources[0x22]	6781	1			T4	6		T8	5		T30	2
valid_sources[0x23]	6677	1			T2	137		T3	1		T4	11
valid_sources[0x24]	6623	1			T3	8		T25	1		T4	13
valid_sources[0x25]	6707	1			T3	7		T4	5		T30	3
valid_sources[0x26]	17771	1			T3	7		T4	4		T8	16
valid_sources[0x27]	17966	1			T1	8		T3	1		T25	1
valid_sources[0x28]	10785	1			T3	7		T4	6		T8	16
valid_sources[0x29]	14182	1			T2	44		T3	2		T4	9
valid_sources[0x2a]	7023	1			T3	2		T25	1		T4	5
valid_sources[0x2b]	6842	1			T3	6		T4	11		T30	12
valid_sources[0x2c]	12895	1			T3	5		T25	1		T4	7
valid_sources[0x2d]	7134	1			T6	3		T2	15		T3	6
valid_sources[0x2e]	6916	1			T4	5		T10	3		T7	6
valid_sources[0x2f]	6810	1			T3	1		T4	5		T30	3
valid_sources[0x30]	6624	1			T2	88		T3	2		T4	12
valid_sources[0x31]	11374	1			T4	12		T7	5		T30	2
valid_sources[0x32]	9522	1			T3	2		T4	2		T10	1
valid_sources[0x33]	6681	1			T2	1		T3	8		T4	5
valid_sources[0x34]	6902	1			T3	3		T25	1		T4	5
valid_sources[0x35]	6529	1			T3	5		T4	12		T10	2
valid_sources[0x36]	6886	1			T3	1		T4	2		T7	1
valid_sources[0x37]	15735	1			T2	65		T4	9		T10	2
valid_sources[0x38]	11192	1			T3	5		T4	7		T10	1
valid_sources[0x39]	12149	1			T4	6		T10	1		T7	28
valid_sources[0x3a]	11894	1			T2	10		T3	20		T4	10
valid_sources[0x3b]	12882	1			T3	2		T25	1		T4	7
valid_sources[0x3c]	6520	1			T3	1		T4	5		T31	4
valid_sources[0x3d]	7133	1			T3	3		T4	8		T10	4
valid_sources[0x3e]	6922	1			T1	9		T3	2		T4	6
valid_sources[0x3f]	6827	1			T3	5		T4	6		T31	2
valid_sources[0x40]	7677	1			T1	15		T4	9		T30	2
valid_sources[0x41]	10489	1			T2	1		T3	1		T4	9
valid_sources[0x42]	7398	1			T1	87		T2	1		T3	7
valid_sources[0x43]	7204	1			T3	3		T4	3		T10	1
valid_sources[0x44]	7294	1			T6	2		T3	8		T4	4
valid_sources[0x45]	6769	1			T3	3		T25	1		T4	6
valid_sources[0x46]	9103	1			T3	8		T25	2		T4	1
valid_sources[0x47]	6899	1			T6	1		T3	3		T4	6
valid_sources[0x48]	7493	1			T2	2		T3	4		T4	6
valid_sources[0x49]	6795	1			T3	10		T25	1		T4	9
valid_sources[0x4a]	7521	1			T4	5		T31	11		T29	2
valid_sources[0x4b]	11096	1			T2	42		T3	1		T4	5
valid_sources[0x4c]	7229	1			T1	16		T3	6		T4	4
valid_sources[0x4d]	6678	1			T3	4		T4	7		T10	9
valid_sources[0x4e]	6743	1			T3	7		T4	2		T11	4
valid_sources[0x4f]	11687	1			T3	4		T4	6		T10	1
valid_sources[0x50]	24167	1			T1	28		T2	1		T3	1
valid_sources[0x51]	19632	1			T4	5		T64	2		T31	6
valid_sources[0x52]	7455	1			T3	2		T4	7		T30	3
valid_sources[0x53]	9889	1			T3	5		T4	10		T31	1
valid_sources[0x54]	7390	1			T6	1		T3	3		T4	7
valid_sources[0x55]	13296	1			T3	2		T4	7		T8	9
valid_sources[0x56]	8437	1			T3	2		T4	14		T10	1
valid_sources[0x57]	11064	1			T1	28		T6	1		T3	5
valid_sources[0x58]	9546	1			T4	7		T30	4		T31	3
valid_sources[0x59]	7203	1			T3	3		T4	9		T31	3
valid_sources[0x5a]	7864	1			T1	1		T3	2		T4	5
valid_sources[0x5b]	6736	1			T3	2		T25	1		T4	7
valid_sources[0x5c]	22701	1			T1	4		T3	6		T4	11
valid_sources[0x5d]	6773	1			T4	7		T9	8		T29	3
valid_sources[0x5e]	6695	1			T3	3		T4	10		T11	1
valid_sources[0x5f]	6358	1			T3	6		T4	1		T31	7
valid_sources[0x60]	6783	1			T3	1		T4	4		T30	1
valid_sources[0x61]	6483	1			T4	7		T11	1		T8	6
valid_sources[0x62]	9939	1			T1	14		T3	3		T4	13
valid_sources[0x63]	11823	1			T3	2		T30	4		T31	7
valid_sources[0x64]	6408	1			T3	6		T4	7		T8	1
valid_sources[0x65]	7533	1			T2	32		T3	8		T4	6
valid_sources[0x66]	14334	1			T3	3		T4	3		T10	1
valid_sources[0x67]	9246	1			T3	2		T4	11		T11	1
valid_sources[0x68]	9420	1			T1	31		T3	2		T4	7
valid_sources[0x69]	9537	1			T3	3		T4	5		T30	5
valid_sources[0x6a]	11885	1			T4	7		T64	1		T30	1
valid_sources[0x6b]	6817	1			T3	6		T4	7		T7	27
valid_sources[0x6c]	6862	1			T3	8		T4	4		T26	5
valid_sources[0x6d]	6907	1			T3	2		T4	5		T30	3
valid_sources[0x6e]	6877	1			T3	4		T4	8		T7	3
valid_sources[0x6f]	15560	1			T1	43		T3	2		T4	3
valid_sources[0x70]	6512	1			T25	2		T4	3		T11	1
valid_sources[0x71]	6644	1			T2	116		T3	10		T4	5
valid_sources[0x72]	6857	1			T3	3		T4	8		T10	2
valid_sources[0x73]	6848	1			T3	1		T4	2		T7	2
valid_sources[0x74]	8517	1			T3	9		T4	7		T10	1
valid_sources[0x75]	6941	1			T3	12		T4	9		T11	1
valid_sources[0x76]	12477	1			T6	1		T3	7		T4	6
valid_sources[0x77]	10763	1			T2	2		T3	3		T4	9
valid_sources[0x78]	6889	1			T1	5		T2	31		T3	2
valid_sources[0x79]	9431	1			T3	5		T4	15		T10	4
valid_sources[0x7a]	10339	1			T1	14		T2	110		T3	2
valid_sources[0x7b]	8223	1			T3	2		T4	5		T11	1
valid_sources[0x7c]	6508	1			T3	3		T25	1		T4	11
valid_sources[0x7d]	10678	1			T3	3		T25	1		T4	4
valid_sources[0x7e]	7020	1			T3	4		T25	1		T4	4
valid_sources[0x7f]	6701	1			T2	1		T3	1		T4	7
valid_sources[0x80]	7429	1			T4	4		T7	4		T30	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

994841

1

T5

12

T1

65

T6

11

values[0x0]

all_enables

biggest_size

73499

1

T5

1

T1

109

T6

3

values[0x1]

all_enables

biggest_size

53817

1

T5

2

T1

126

T6

3