Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31360	1			T1	54		T3	9		T4	88
auto[PWRUP]	119	1			T15	1		T24	1		T91	2
auto[ONEST_0]	81	1			T18	2		T91	1		T35	3
auto[ONEST_021]	21	1			T24	2		T35	1		T193	1
auto[ONEST_1]	78	1			T15	3		T18	2		T93	1
auto[ONEST_DONE]	4	1			T194	1		T195	1		T196	1
auto[LP_0]	124	1			T15	3		T18	3		T93	2
auto[LP_021]	29	1			T35	1		T193	1		T197	1
auto[LP_1]	126	1			T15	2		T18	2		T93	1
auto[LP_EVAL]	66	1			T15	2		T18	2		T93	2
auto[LP_SLP]	504	1			T15	16		T18	8		T24	3
auto[LP_PWRUP]	22	1			T197	1		T198	1		T199	1
auto[NP_0]	164	1			T15	2		T18	4		T93	2
auto[NP_021]	36	1			T18	1		T200	3		T197	1
auto[NP_1]	154	1			T15	2		T18	1		T93	3
auto[NP_EVAL]	32	1			T15	2		T18	1		T200	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T93

1

T197

1

T187

1

min

30824

1

T1

54

T3

9

T4

88

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30830	1			T1	54		T3	9		T4	88
pow[0x1]	8	1			T201	1		T202	1		T203	1
pow[0x2]	18	1			T18	1		T193	1		T204	1
pow[0x3]	45	1			T15	1		T18	1		T35	3
pow[0x4]	64	1			T15	2		T18	1		T35	3
pow[0x5]	149	1			T15	1		T18	1		T93	3
pow[0x6]	255	1			T15	3		T18	4		T24	2
pow[0x7]	487	1			T15	4		T18	12		T93	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

209

1

T15

7

T18

2

T24

2

min

30364

1

T1

54

T3

9

T4

88

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30364	1			T1	54		T3	9		T4	88
pow[0x4]	4	1			T18	1		T205	1		T160	1
pow[0x5]	1	1			T206	1		-	-		-	-
pow[0x6]	2	1			T93	1		T207	1		-	-
pow[0x7]	6	1			T193	1		T166	1		T194	1
pow[0x8]	7	1			T208	1		T209	1		T210	1
pow[0x9]	6	1			T167	1		T209	1		T211	1
pow[0xa]	18	1			T200	1		T212	1		T194	1
pow[0xb]	39	1			T15	2		T35	1		T204	1
pow[0xc]	76	1			T18	2		T193	2		T200	4
pow[0xd]	114	1			T18	2		T35	1		T193	3
pow[0xe]	282	1			T15	4		T18	6		T93	3
pow[0xf]	571	1			T15	13		T18	8		T24	2