Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2327	1			T1	10		T2	20		T3	10
auto[PWRUP]	123	1			T15	2		T18	2		T24	1
auto[ONEST_0]	77	1			T15	1		T18	1		T91	1
auto[ONEST_021]	17	1			T96	1		T198	1		T365	1
auto[ONEST_1]	80	1			T15	1		T18	2		T91	1
auto[ONEST_DONE]	7	1			T193	1		T285	1		T201	1
auto[LP_0]	109	1			T18	1		T91	1		T35	3
auto[LP_021]	28	1			T15	1		T18	1		T193	1
auto[LP_1]	120	1			T15	2		T18	2		T24	1
auto[LP_EVAL]	67	1			T15	2		T18	1		T91	1
auto[LP_SLP]	513	1			T15	4		T18	6		T24	3
auto[LP_PWRUP]	30	1			T92	1		T173	1		T164	1
auto[NP_0]	218	1			T15	1		T18	1		T24	3
auto[NP_021]	55	1			T15	1		T35	3		T200	1
auto[NP_1]	232	1			T15	1		T18	1		T24	2
auto[NP_EVAL]	33	1			T24	1		T91	1		T197	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T366

1

T367

1

T368

1

min

1948

1

T1

10

T2

20

T3

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1963	1			T1	10		T2	20		T3	10
pow[0x1]	13	1			T208	1		T199	1		T369	1
pow[0x2]	24	1			T164	1		T167	1		T370	1
pow[0x3]	35	1			T15	1		T24	1		T93	1
pow[0x4]	64	1			T18	2		T91	1		T35	2
pow[0x5]	133	1			T15	1		T18	1		T93	1
pow[0x6]	263	1			T15	3		T24	1		T35	7
pow[0x7]	529	1			T15	12		T18	4		T24	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

190

1

T15

5

T18

2

T93

1

min

1361

1

T1

10

T2

20

T3

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1364	1			T1	10		T2	20		T3	10
pow[0x1]	25	1			T91	1		T166	3		T186	1
pow[0x2]	32	1			T227	1		T285	5		T235	2
pow[0x3]	50	1			T24	2		T35	1		T140	2
pow[0x4]	51	1			T24	2		T91	3		T35	1
pow[0x5]	1	1			T371	1		-	-		-	-
pow[0x7]	2	1			T212	1		T368	1		-	-
pow[0x8]	4	1			T246	1		T368	1		T207	1
pow[0x9]	12	1			T24	1		T35	1		T212	1
pow[0xa]	21	1			T18	1		T35	1		T204	1
pow[0xb]	37	1			T15	2		T35	3		T200	1
pow[0xc]	69	1			T18	1		T93	1		T35	1
pow[0xd]	146	1			T18	1		T93	2		T91	2
pow[0xe]	295	1			T15	4		T18	4		T24	3
pow[0xf]	558	1			T15	8		T18	6		T24	2