Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T15,T16,T18

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T20,T93,T97
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T93,T97
0	1	Covered	T20,T93,T97
1	0	Covered	T20,T93,T97

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T20,T21,T34
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T34
0	1	Covered	T20,T21,T34
1	0	Covered	T20,T21,T34

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T21
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T14,T19,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T21,T24,T97
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T97,T34
0	1	Covered	T21,T97,T34
1	0	Covered	T21,T24,T97

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T15,T16
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T14,T20,T21
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T14,T20,T21
1	0	Covered	T14,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T20,T93,T97
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T93,T97
0	1	Covered	T20,T93,T97
1	0	Covered	T20,T93,T97

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T21
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T14,T19,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T21,T24,T97
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T97,T34
0	1	Covered	T21,T97,T34
1	0	Covered	T21,T24,T97

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T15,T16
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T17

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T17
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T17
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T17
1	1	0	Covered	T12,T13,T17
1	1	1	Covered	T12,T13,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T13,T17
1	1	0	Covered	T12,T13,T17
1	1	1	Covered	T12,T13,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T17
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T17

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T16,T18
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T20,T93,T97

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T20,T93,T97

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T20,T21,T34

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T19,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T19,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T21,T24,T97

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T21,T24,T97

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T17

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31477176	31170501	0	0
gen_filter_match[0].MatchCheck00_A	31477176	9334218	0	0
gen_filter_match[0].MatchCheck01_A	31477176	2428603	0	0
gen_filter_match[0].MatchCheck10_A	31477176	2135526	0	0
gen_filter_match[0].MatchCheck11_A	31477176	17272154	0	0
gen_filter_match[1].MatchCheck00_A	31477176	10379285	0	0
gen_filter_match[1].MatchCheck01_A	31477176	1133571	0	0
gen_filter_match[1].MatchCheck10_A	31477176	1094063	0	0
gen_filter_match[1].MatchCheck11_A	31477176	18563582	0	0
gen_filter_match[2].MatchCheck00_A	31477176	11607075	0	0
gen_filter_match[2].MatchCheck01_A	31477176	524297	0	0
gen_filter_match[2].MatchCheck10_A	31477176	719139	0	0
gen_filter_match[2].MatchCheck11_A	31477176	18319990	0	0
gen_filter_match[3].MatchCheck00_A	31477176	12560666	0	0
gen_filter_match[3].MatchCheck01_A	31477176	307656	0	0
gen_filter_match[3].MatchCheck10_A	31477176	256370	0	0
gen_filter_match[3].MatchCheck11_A	31477176	18045809	0	0
gen_filter_match[4].MatchCheck00_A	31477176	12026413	0	0
gen_filter_match[4].MatchCheck01_A	31477176	3154	0	0
gen_filter_match[4].MatchCheck10_A	31477176	66361	0	0
gen_filter_match[4].MatchCheck11_A	31477176	19074573	0	0
gen_filter_match[5].MatchCheck00_A	31477176	11940984	0	0
gen_filter_match[5].MatchCheck01_A	31477176	33732	0	0
gen_filter_match[5].MatchCheck10_A	31477176	84	0	0
gen_filter_match[5].MatchCheck11_A	31477176	19195701	0	0
gen_filter_match[6].MatchCheck00_A	31477176	12504181	0	0
gen_filter_match[6].MatchCheck01_A	31477176	32434	0	0
gen_filter_match[6].MatchCheck10_A	31477176	32301	0	0
gen_filter_match[6].MatchCheck11_A	31477176	18601585	0	0
gen_filter_match[7].MatchCheck00_A	31477176	12288324	0	0
gen_filter_match[7].MatchCheck01_A	31477176	175532	0	0
gen_filter_match[7].MatchCheck10_A	31477176	297678	0	0
gen_filter_match[7].MatchCheck11_A	31477176	18408967	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	31170501	0	0
T12	66265	66207	0	0
T13	33192	33100	0	0
T14	33674	33605	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	66312	0	0
T18	23568	21380	0	0
T19	65135	65079	0	0
T20	64901	64802	0	0
T27	83	7	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	9334218	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	21734	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	20647	0	0
T19	65135	33028	0	0
T20	64901	32197	0	0
T27	83	7	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	2428603	0	0
T21	97984	32511	0	0
T22	33433	0	0	0
T23	31934	0	0	0
T24	37237	20227	0	0
T40	114	0	0	0
T55	32955	0	0	0
T92	0	32780	0	0
T93	55957	0	0	0
T96	0	9120	0	0
T98	32303	32222	0	0
T99	0	31605	0	0
T100	0	33520	0	0
T101	0	32856	0	0
T102	0	33120	0	0
T103	0	32406	0	0
T104	67058	0	0	0
T105	67050	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	2135526	0	0
T19	65135	32051	0	0
T20	64901	0	0	0
T21	97984	33092	0	0
T22	33433	0	0	0
T23	31934	0	0	0
T24	37237	0	0	0
T39	62	0	0	0
T40	114	0	0	0
T55	32955	0	0	0
T93	55957	0	0	0
T100	0	32977	0	0
T102	0	33151	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	32686	0	0
T110	0	33171	0	0
T111	0	32658	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	17272154	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	33601	0	0
T15	25481	795	0	0
T16	1042	0	0	0
T17	66363	66309	0	0
T18	23568	733	0	0
T19	65135	0	0	0
T20	64901	32605	0	0
T21	0	32297	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T27	83	0	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	10379285	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	33028	0	0
T20	64901	32608	0	0
T27	83	7	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	1133571	0	0
T14	33674	33601	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	0	0	0
T18	23568	0	0	0
T19	65135	0	0	0
T20	64901	32194	0	0
T21	97984	0	0	0
T24	0	2147	0	0
T27	83	0	0	0
T39	62	0	0	0
T91	0	23533	0	0
T97	0	32913	0	0
T112	0	33224	0	0
T113	0	32689	0	0
T114	0	32909	0	0
T115	0	35106	0	0
T116	0	66104	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	1094063	0	0
T48	0	75013	0	0
T94	1154	0	0	0
T98	32303	0	0	0
T105	67050	1	0	0
T106	66339	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T113	0	32927	0	0
T114	0	32416	0	0
T117	32698	32603	0	0
T118	0	32593	0	0
T119	0	1	0	0
T120	5110	0	0	0
T121	66457	0	0	0
T122	66681	0	0	0
T123	8740	0	0	0
T124	6843	0	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	18563582	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	0	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66309	0	0
T18	23568	0	0	0
T19	65135	32051	0	0
T20	64901	0	0	0
T21	0	64808	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T27	83	0	0	0
T55	0	32880	0	0
T93	0	31494	0	0
T104	0	66997	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	11607075	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	33605	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	32054	0	0
T20	64901	32197	0	0
T27	83	7	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	524297	0	0
T42	1630	0	0	0
T110	65961	0	0	0
T125	98004	32740	0	0
T126	0	33404	0	0
T127	0	32802	0	0
T128	0	33682	0	0
T129	0	32480	0	0
T130	0	32309	0	0
T131	0	3	0	0
T132	0	32281	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	32758	0	0	0
T136	31565	0	0	0
T137	34000	0	0	0
T138	96712	0	0	0
T139	71221	0	0	0
T140	10804	0	0	0
T141	832	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	719139	0	0
T91	0	5	0	0
T92	0	32158	0	0
T94	1154	0	0	0
T98	32303	0	0	0
T102	0	65218	0	0
T105	67050	1	0	0
T106	66339	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T117	32698	0	0	0
T120	5110	0	0	0
T121	66457	0	0	0
T122	66681	0	0	0
T123	8740	0	0	0
T124	6843	0	0	0
T125	0	65183	0	0
T142	0	32842	0	0
T143	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	18319990	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	0	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66309	0	0
T18	23568	0	0	0
T19	65135	33025	0	0
T20	64901	32605	0	0
T21	0	97900	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	22375	0	0
T27	83	0	0	0
T55	0	32880	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	12560666	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	3	0	0
T20	64901	3	0	0
T27	83	7	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	307656	0	0
T109	66480	0	0	0
T113	98362	32675	0	0
T114	0	32745	0	0
T119	0	1	0	0
T142	64633	0	0	0
T144	66198	32524	0	0
T145	0	3	0	0
T146	0	1	0	0
T147	0	34624	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	32729	0	0
T151	71	0	0	0
T152	1091	0	0	0
T153	794	0	0	0
T154	78	0	0	0
T155	82750	0	0	0
T156	66918	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	256370	0	0
T17	66363	1	0	0
T18	23568	0	0	0
T19	65135	33025	0	0
T20	64901	0	0	0
T21	97984	0	0	0
T22	33433	0	0	0
T23	31934	0	0	0
T24	37237	0	0	0
T39	62	0	0	0
T40	114	0	0	0
T91	0	5	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T119	0	1	0	0
T143	0	1	0	0
T157	0	32821	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	18045809	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	33601	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66308	0	0
T18	23568	0	0	0
T19	65135	32051	0	0
T20	64901	64799	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	20228	0	0
T27	83	0	0	0
T55	0	32880	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	12026413	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	32054	0	0
T20	64901	32197	0	0
T27	83	7	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	3154	0	0
T48	75096	1	0	0
T133	0	1	0	0
T145	64331	2	0	0
T146	66785	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T158	66939	1	0	0
T159	0	1	0	0
T160	0	3139	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	7442	0	0	0
T164	21854	0	0	0
T165	1126	0	0	0
T166	12480	0	0	0
T167	54117	0	0	0
T168	66631	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	66361	0	0
T17	66363	1	0	0
T18	23568	0	0	0
T19	65135	0	0	0
T20	64901	0	0	0
T21	97984	0	0	0
T22	33433	0	0	0
T23	31934	0	0	0
T24	37237	0	0	0
T39	62	0	0	0
T40	114	0	0	0
T48	0	1	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T158	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	19074573	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	33601	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66308	0	0
T18	23568	0	0	0
T19	65135	33025	0	0
T20	64901	32605	0	0
T21	0	64808	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	22375	0	0
T27	83	0	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	11940984	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	32054	0	0
T20	64901	3	0	0
T27	83	7	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	33732	0	0
T119	65548	1	0	0
T125	98004	0	0	0
T129	0	32482	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	32758	0	0	0
T145	0	3	0	0
T148	0	1	0	0
T149	0	1	0	0
T169	0	1234	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	1198	0	0	0
T173	19060	0	0	0
T174	65099	0	0	0
T175	1139	0	0	0
T176	65943	0	0	0
T177	86	0	0	0
T178	65538	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	84	0	0
T17	66363	1	0	0
T18	23568	0	0	0
T19	65135	0	0	0
T20	64901	0	0	0
T21	97984	0	0	0
T22	33433	0	0	0
T23	31934	0	0	0
T24	37237	0	0	0
T39	62	0	0	0
T40	114	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T119	0	1	0	0
T143	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	19195701	0	0
T12	66265	66204	0	0
T13	33192	33096	0	0
T14	33674	33601	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66308	0	0
T18	23568	0	0	0
T19	65135	33025	0	0
T20	64901	64799	0	0
T21	0	97900	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	20228	0	0
T27	83	0	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	12504181	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	4	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	3	0	0
T20	64901	32608	0	0
T27	83	7	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	32434	0	0
T48	75096	1	0	0
T128	0	1	0	0
T134	0	2	0	0
T145	64331	3	0	0
T146	66785	0	0	0
T149	0	1	0	0
T164	21854	0	0	0
T165	1126	0	0	0
T166	12480	0	0	0
T167	54117	0	0	0
T168	66631	0	0	0
T170	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	32416	0	0
T184	0	1	0	0
T185	1150	0	0	0
T186	187088	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	32301	0	0
T13	33192	1	0	0
T14	33674	0	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	1	0	0
T18	23568	0	0	0
T19	65135	0	0	0
T20	64901	0	0	0
T27	83	0	0	0
T39	62	0	0	0
T48	0	1	0	0
T91	0	5	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T119	0	1	0	0
T143	0	1	0	0
T158	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	18601585	0	0
T12	66265	66204	0	0
T13	33192	33095	0	0
T14	33674	33601	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66308	0	0
T18	23568	0	0	0
T19	65135	65076	0	0
T20	64901	32194	0	0
T21	0	65389	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	22375	0	0
T27	83	0	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	12288324	0	0
T12	66265	3	0	0
T13	33192	4	0	0
T14	33674	33605	0	0
T15	25481	22529	0	0
T16	1042	961	0	0
T17	66363	3	0	0
T18	23568	21380	0	0
T19	65135	32054	0	0
T20	64901	32608	0	0
T27	83	7	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	175532	0	0
T116	0	33435	0	0
T145	64331	0	0	0
T146	66785	33922	0	0
T148	0	1	0	0
T158	66939	1	0	0
T163	7442	0	0	0
T164	21854	0	0	0
T165	1126	0	0	0
T166	12480	0	0	0
T167	54117	0	0	0
T168	66631	0	0	0
T170	0	1	0	0
T171	0	3	0	0
T181	0	1	0	0
T182	0	1	0	0
T185	1150	0	0	0
T187	0	12784	0	0
T188	0	33688	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	297678	0	0
T13	33192	1	0	0
T14	33674	0	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	1	0	0
T18	23568	0	0	0
T19	65135	0	0	0
T20	64901	0	0	0
T27	83	0	0	0
T39	62	0	0	0
T91	0	5	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T108	0	2	0	0
T143	0	1	0	0
T145	0	3	0	0
T158	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31477176	18408967	0	0
T12	66265	66204	0	0
T13	33192	33095	0	0
T14	33674	0	0	0
T15	25481	0	0	0
T16	1042	0	0	0
T17	66363	66308	0	0
T18	23568	0	0	0
T19	65135	33025	0	0
T20	64901	32194	0	0
T21	0	97900	0	0
T22	0	33352	0	0
T23	0	31866	0	0
T24	0	20228	0	0
T27	83	0	0	0
T55	0	32880	0	0