Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7450	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1849	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1713	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1925	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1968	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1899	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1764	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1751	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1787	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1810	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1861	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1644	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1759	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1906	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1894	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1798	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1752	0	0
adc_en_ctl_rd_A	2147483647	1322	0	0
adc_fsm_rst_rd_A	2147483647	1127	0	0
adc_intr_ctl_rd_A	2147483647	1285	0	0
adc_lp_sample_ctl_rd_A	2147483647	1323	0	0
adc_pd_ctl_rd_A	2147483647	1619	0	0
adc_sample_ctl_rd_A	2147483647	1144	0	0
adc_wakeup_ctl_rd_A	2147483647	1178	0	0
intr_enable_rd_A	2147483647	1533	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7450	0	0
T9	230915	0	0	0
T30	231006	2	0	0
T31	833906	1	0	0
T32	46757	0	0	0
T36	12682	573	0	0
T37	47018	271	0	0
T56	646885	2	0	0
T57	0	155	0	0
T58	0	258	0	0
T60	0	631	0	0
T62	0	439	0	0
T65	11988	0	0	0
T189	0	1	0	0
T190	13253	0	0	0
T191	5268	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1849	0	0
T1	27205	91	0	0
T2	855923	0	0	0
T3	167904	128	0	0
T4	72868	207	0	0
T6	29811	0	0	0
T7	404714	51	0	0
T10	14021	11	0	0
T11	10796	3	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	93	0	0
T31	0	115	0	0
T37	0	2	0	0
T192	0	10	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1713	0	0
T1	27205	89	0	0
T2	855923	0	0	0
T3	167904	111	0	0
T4	72868	207	0	0
T6	29811	0	0	0
T7	404714	46	0	0
T10	14021	0	0	0
T11	10796	2	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	61	0	0
T31	0	109	0	0
T37	0	32	0	0
T57	0	20	0	0
T192	0	10	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1925	0	0
T1	27205	153	0	0
T2	855923	0	0	0
T3	167904	128	0	0
T4	72868	242	0	0
T6	29811	0	0	0
T7	404714	26	0	0
T10	14021	2	0	0
T11	10796	3	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	58	0	0
T31	0	100	0	0
T37	0	9	0	0
T192	0	14	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1968	0	0
T1	27205	141	0	0
T2	855923	0	0	0
T3	167904	124	0	0
T4	72868	231	0	0
T6	29811	0	0	0
T7	404714	25	0	0
T10	14021	2	0	0
T11	10796	8	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	73	0	0
T31	0	102	0	0
T37	0	11	0	0
T192	0	9	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1899	0	0
T1	27205	90	0	0
T2	855923	0	0	0
T3	167904	91	0	0
T4	72868	182	0	0
T6	29811	0	0	0
T7	404714	48	0	0
T10	14021	7	0	0
T11	10796	30	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	39	0	0
T31	0	114	0	0
T37	0	14	0	0
T192	0	11	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1764	0	0
T1	27205	108	0	0
T2	855923	0	0	0
T3	167904	96	0	0
T4	72868	205	0	0
T6	29811	0	0	0
T7	404714	18	0	0
T10	14021	10	0	0
T11	10796	1	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	63	0	0
T31	0	116	0	0
T37	0	30	0	0
T192	0	7	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1751	0	0
T1	27205	128	0	0
T2	855923	0	0	0
T3	167904	132	0	0
T4	72868	194	0	0
T6	29811	0	0	0
T7	404714	38	0	0
T10	14021	2	0	0
T11	10796	11	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	76	0	0
T31	0	92	0	0
T37	0	6	0	0
T192	0	5	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1787	0	0
T1	27205	96	0	0
T2	855923	0	0	0
T3	167904	103	0	0
T4	72868	153	0	0
T6	29811	0	0	0
T7	404714	50	0	0
T10	14021	0	0	0
T11	10796	4	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	47	0	0
T31	0	142	0	0
T37	0	45	0	0
T57	0	4	0	0
T192	0	6	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T1	27205	105	0	0
T2	855923	0	0	0
T3	167904	136	0	0
T4	72868	201	0	0
T6	29811	0	0	0
T7	404714	17	0	0
T10	14021	6	0	0
T11	10796	25	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	81	0	0
T31	0	55	0	0
T37	0	34	0	0
T192	0	15	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1861	0	0
T1	27205	134	0	0
T2	855923	0	0	0
T3	167904	97	0	0
T4	72868	172	0	0
T6	29811	0	0	0
T7	404714	31	0	0
T10	14021	7	0	0
T11	10796	6	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	67	0	0
T31	0	60	0	0
T37	0	6	0	0
T192	0	10	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1644	0	0
T1	27205	72	0	0
T2	855923	0	0	0
T3	167904	96	0	0
T4	72868	151	0	0
T6	29811	0	0	0
T7	404714	21	0	0
T10	14021	2	0	0
T11	10796	3	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	73	0	0
T31	0	89	0	0
T37	0	37	0	0
T192	0	5	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1759	0	0
T1	27205	76	0	0
T2	855923	0	0	0
T3	167904	101	0	0
T4	72868	177	0	0
T6	29811	0	0	0
T7	404714	12	0	0
T10	14021	3	0	0
T11	10796	8	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	78	0	0
T31	0	84	0	0
T37	0	54	0	0
T192	0	1	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1906	0	0
T1	27205	120	0	0
T2	855923	0	0	0
T3	167904	153	0	0
T4	72868	175	0	0
T6	29811	0	0	0
T7	404714	47	0	0
T10	14021	5	0	0
T11	10796	10	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	89	0	0
T31	0	106	0	0
T37	0	27	0	0
T192	0	5	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894	0	0
T1	27205	120	0	0
T2	855923	0	0	0
T3	167904	93	0	0
T4	72868	189	0	0
T6	29811	0	0	0
T7	404714	55	0	0
T10	14021	2	0	0
T11	10796	11	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	50	0	0
T31	0	181	0	0
T37	0	22	0	0
T192	0	10	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1798	0	0
T1	27205	116	0	0
T2	855923	0	0	0
T3	167904	68	0	0
T4	72868	193	0	0
T6	29811	0	0	0
T7	404714	57	0	0
T10	14021	3	0	0
T11	10796	2	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	38	0	0
T31	0	113	0	0
T37	0	5	0	0
T192	0	6	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1752	0	0
T1	27205	95	0	0
T2	855923	0	0	0
T3	167904	104	0	0
T4	72868	207	0	0
T6	29811	0	0	0
T7	404714	30	0	0
T10	14021	1	0	0
T11	10796	3	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	60	0	0
T31	0	80	0	0
T37	0	37	0	0
T192	0	17	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322	0	0
T1	27205	62	0	0
T2	855923	0	0	0
T3	167904	39	0	0
T4	72868	120	0	0
T6	29811	0	0	0
T7	404714	13	0	0
T10	14021	9	0	0
T11	10796	4	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	31	0	0
T31	0	41	0	0
T37	0	27	0	0
T192	0	9	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1127	0	0
T1	27205	32	0	0
T2	855923	0	0	0
T3	167904	49	0	0
T4	72868	78	0	0
T6	29811	0	0	0
T7	404714	57	0	0
T10	14021	3	0	0
T11	10796	1	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	15	0	0
T31	0	51	0	0
T37	0	38	0	0
T192	0	16	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1285	0	0
T1	27205	42	0	0
T2	855923	0	0	0
T3	167904	34	0	0
T4	72868	94	0	0
T6	29811	0	0	0
T7	404714	28	0	0
T10	14021	5	0	0
T11	10796	8	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	13	0	0
T31	0	72	0	0
T37	0	41	0	0
T192	0	9	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1323	0	0
T1	27205	65	0	0
T2	855923	0	0	0
T3	167904	35	0	0
T4	72868	74	0	0
T6	29811	0	0	0
T7	404714	38	0	0
T10	14021	13	0	0
T11	10796	1	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	35	0	0
T31	0	55	0	0
T37	0	43	0	0
T192	0	9	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619	0	0
T1	27205	100	0	0
T2	855923	0	0	0
T3	167904	70	0	0
T4	72868	164	0	0
T6	29811	0	0	0
T7	404714	19	0	0
T10	14021	9	0	0
T11	10796	24	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	40	0	0
T31	0	64	0	0
T37	0	36	0	0
T192	0	3	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T1	27205	65	0	0
T2	855923	0	0	0
T3	167904	23	0	0
T4	72868	73	0	0
T6	29811	0	0	0
T7	404714	12	0	0
T10	14021	2	0	0
T11	10796	2	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	37	0	0
T31	0	36	0	0
T37	0	30	0	0
T192	0	1	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T1	27205	26	0	0
T2	855923	0	0	0
T3	167904	30	0	0
T4	72868	94	0	0
T6	29811	0	0	0
T7	404714	41	0	0
T10	14021	15	0	0
T11	10796	7	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	18	0	0
T31	0	69	0	0
T37	0	47	0	0
T192	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1533	0	0
T1	27205	54	0	0
T2	855923	0	0	0
T3	167904	49	0	0
T4	72868	78	0	0
T6	29811	13	0	0
T7	404714	28	0	0
T10	14021	10	0	0
T11	10796	1	0	0
T25	80738	0	0	0
T26	30401	0	0	0
T30	0	35	0	0
T63	0	28	0	0
T64	0	30	0	0