Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1171822	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1129844

1

T1

55

T2

4570

T3

606

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2012899	1			T1	120		T2	3581		T3	1127
values[0x0]	143958	1			T1	27		T2	1715		T3	272
values[0x1]	144809	1			T1	32		T2	1867		T3	308

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	943711	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1357955

1

T1

105

T2

5026

T3

1033

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7313	1			T2	32		T3	4		T4	3
valid_sources[0x01]	7440	1			T1	1		T2	19		T3	15
valid_sources[0x02]	12033	1			T2	39		T3	11		T4	2
valid_sources[0x03]	11412	1			T2	27		T3	7		T4	5
valid_sources[0x04]	7509	1			T2	28		T3	1		T4	5
valid_sources[0x05]	6892	1			T1	2		T2	31		T3	10
valid_sources[0x06]	7081	1			T2	16		T3	1		T4	1
valid_sources[0x07]	9588	1			T1	1		T2	28		T3	21
valid_sources[0x08]	6632	1			T2	25		T3	5		T4	2
valid_sources[0x09]	7141	1			T2	13		T3	3		T4	4
valid_sources[0x0a]	7493	1			T2	13		T3	14		T4	4
valid_sources[0x0b]	9545	1			T2	23		T3	7		T4	2
valid_sources[0x0c]	7499	1			T2	22		T3	4		T4	2
valid_sources[0x0d]	7068	1			T2	36		T3	18		T4	3
valid_sources[0x0e]	6410	1			T2	29		T3	9		T4	3
valid_sources[0x0f]	15857	1			T1	1		T2	15		T3	1
valid_sources[0x10]	15240	1			T2	37		T3	4		T4	5
valid_sources[0x11]	15430	1			T2	6		T3	6		T4	4
valid_sources[0x12]	11075	1			T2	42		T3	8		T23	3
valid_sources[0x13]	6536	1			T1	1		T2	23		T4	4
valid_sources[0x14]	7385	1			T1	1		T2	17		T3	13
valid_sources[0x15]	6864	1			T1	1		T2	31		T3	6
valid_sources[0x16]	6737	1			T2	20		T3	9		T4	5
valid_sources[0x17]	11515	1			T1	3		T2	15		T3	16
valid_sources[0x18]	10804	1			T2	26		T3	6		T4	5
valid_sources[0x19]	7266	1			T1	1		T2	40		T3	4
valid_sources[0x1a]	8998	1			T2	16		T3	13		T4	4
valid_sources[0x1b]	12324	1			T2	20		T4	2		T22	1
valid_sources[0x1c]	6949	1			T2	19		T3	2		T4	1
valid_sources[0x1d]	16515	1			T2	29		T3	6		T4	5
valid_sources[0x1e]	11263	1			T2	44		T3	5		T4	1
valid_sources[0x1f]	7192	1			T2	29		T3	2		T4	4
valid_sources[0x20]	6715	1			T2	39		T3	3		T4	5
valid_sources[0x21]	6751	1			T1	3		T2	17		T3	10
valid_sources[0x22]	11341	1			T1	1		T2	51		T3	8
valid_sources[0x23]	6799	1			T2	26		T3	11		T4	3
valid_sources[0x24]	15100	1			T1	2		T2	34		T3	7
valid_sources[0x25]	6822	1			T1	1		T2	41		T3	20
valid_sources[0x26]	6843	1			T1	1		T2	21		T3	6
valid_sources[0x27]	6828	1			T2	19		T3	1		T4	8
valid_sources[0x28]	6628	1			T2	24		T3	2		T4	3
valid_sources[0x29]	12807	1			T2	12		T3	12		T4	2
valid_sources[0x2a]	6795	1			T2	48		T3	22		T4	2
valid_sources[0x2b]	8453	1			T1	6		T2	28		T3	15
valid_sources[0x2c]	9457	1			T2	28		T3	13		T4	3
valid_sources[0x2d]	7966	1			T2	19		T3	16		T4	2
valid_sources[0x2e]	7487	1			T1	4		T2	31		T3	10
valid_sources[0x2f]	11253	1			T1	3		T2	20		T3	7
valid_sources[0x30]	11494	1			T1	2		T2	20		T3	5
valid_sources[0x31]	6766	1			T1	2		T2	49		T3	3
valid_sources[0x32]	6884	1			T2	20		T3	2		T4	4
valid_sources[0x33]	7923	1			T2	46		T3	5		T4	4
valid_sources[0x34]	22437	1			T2	12		T3	14		T4	3
valid_sources[0x35]	6889	1			T2	35		T3	1		T4	4
valid_sources[0x36]	6904	1			T2	21		T3	1		T4	4
valid_sources[0x37]	7592	1			T2	29		T3	10		T4	4
valid_sources[0x38]	14111	1			T2	9		T3	3		T4	6
valid_sources[0x39]	10488	1			T2	28		T3	5		T4	5
valid_sources[0x3a]	11949	1			T1	2		T2	30		T4	4
valid_sources[0x3b]	7117	1			T2	22		T3	7		T4	2
valid_sources[0x3c]	7044	1			T1	1		T2	22		T3	4
valid_sources[0x3d]	11141	1			T1	2		T2	21		T3	4
valid_sources[0x3e]	7607	1			T2	10		T3	7		T4	1
valid_sources[0x3f]	7338	1			T2	19		T4	1		T34	1
valid_sources[0x40]	17954	1			T2	41		T3	5		T4	4
valid_sources[0x41]	6720	1			T2	28		T3	1		T4	1
valid_sources[0x42]	6819	1			T2	9		T3	8		T4	6
valid_sources[0x43]	10952	1			T1	1		T2	21		T3	6
valid_sources[0x44]	7173	1			T2	25		T3	3		T4	5
valid_sources[0x45]	9916	1			T2	42		T3	8		T4	4
valid_sources[0x46]	6898	1			T2	21		T3	7		T4	4
valid_sources[0x47]	6701	1			T1	2		T2	16		T3	6
valid_sources[0x48]	6999	1			T2	15		T3	8		T4	5
valid_sources[0x49]	6709	1			T2	14		T3	10		T4	3
valid_sources[0x4a]	11894	1			T2	15		T3	5		T4	1
valid_sources[0x4b]	11119	1			T2	36		T3	6		T4	1
valid_sources[0x4c]	8025	1			T2	27		T3	5		T4	1
valid_sources[0x4d]	9493	1			T2	35		T3	6		T4	2
valid_sources[0x4e]	6915	1			T2	11		T3	9		T4	6
valid_sources[0x4f]	7072	1			T2	26		T4	4		T23	1
valid_sources[0x50]	6649	1			T1	2		T2	30		T3	3
valid_sources[0x51]	7538	1			T1	2		T2	33		T3	16
valid_sources[0x52]	6745	1			T2	49		T3	8		T4	5
valid_sources[0x53]	12889	1			T1	1		T2	46		T3	9
valid_sources[0x54]	9645	1			T1	2		T2	32		T3	5
valid_sources[0x55]	13954	1			T1	1		T2	13		T4	3
valid_sources[0x56]	7151	1			T2	19		T3	9		T4	3
valid_sources[0x57]	14105	1			T2	20		T3	11		T4	5
valid_sources[0x58]	7391	1			T1	1		T2	22		T3	2
valid_sources[0x59]	13106	1			T2	19		T3	4		T4	2
valid_sources[0x5a]	12836	1			T2	24		T3	6		T4	5
valid_sources[0x5b]	12441	1			T1	1		T2	16		T3	8
valid_sources[0x5c]	7649	1			T2	16		T3	10		T4	1
valid_sources[0x5d]	8719	1			T1	2		T2	52		T3	3
valid_sources[0x5e]	11267	1			T2	25		T3	5		T4	3
valid_sources[0x5f]	9411	1			T2	18		T3	4		T4	3
valid_sources[0x60]	6663	1			T1	2		T2	26		T3	2
valid_sources[0x61]	7051	1			T1	1		T2	26		T3	4
valid_sources[0x62]	7897	1			T2	36		T3	3		T4	1
valid_sources[0x63]	12589	1			T2	35		T3	7		T4	2
valid_sources[0x64]	8125	1			T1	1		T2	21		T3	2
valid_sources[0x65]	9415	1			T1	2		T2	32		T3	5
valid_sources[0x66]	6559	1			T2	44		T3	1		T4	6
valid_sources[0x67]	11588	1			T2	41		T3	3		T4	2
valid_sources[0x68]	10599	1			T2	15		T3	5		T4	3
valid_sources[0x69]	7882	1			T2	39		T4	2		T23	3
valid_sources[0x6a]	6481	1			T1	3		T2	27		T3	3
valid_sources[0x6b]	19634	1			T2	48		T3	2		T4	5
valid_sources[0x6c]	6865	1			T1	5		T2	20		T3	5
valid_sources[0x6d]	7270	1			T1	2		T2	40		T3	6
valid_sources[0x6e]	7528	1			T2	14		T3	3		T4	2
valid_sources[0x6f]	7537	1			T1	1		T2	43		T3	5
valid_sources[0x70]	6732	1			T1	1		T2	38		T3	6
valid_sources[0x71]	7053	1			T2	24		T3	21		T4	5
valid_sources[0x72]	18063	1			T1	1		T2	23		T3	1
valid_sources[0x73]	13919	1			T1	1		T2	38		T3	16
valid_sources[0x74]	6996	1			T1	3		T2	25		T3	6
valid_sources[0x75]	6881	1			T2	51		T3	6		T4	2
valid_sources[0x76]	6819	1			T2	33		T3	3		T4	2
valid_sources[0x77]	6633	1			T1	4		T2	32		T3	3
valid_sources[0x78]	16019	1			T2	22		T3	13		T4	2
valid_sources[0x79]	6725	1			T2	10		T3	9		T4	5
valid_sources[0x7a]	9156	1			T2	56		T3	5		T4	6
valid_sources[0x7b]	7566	1			T2	20		T3	13		T4	2
valid_sources[0x7c]	7115	1			T1	1		T2	31		T3	19
valid_sources[0x7d]	7611	1			T2	31		T3	6		T4	6
valid_sources[0x7e]	8189	1			T1	1		T2	11		T3	1
valid_sources[0x7f]	6751	1			T1	1		T2	21		T3	8
valid_sources[0x80]	6942	1			T1	1		T2	10		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1002473

1

T1

12

T2

1798

T3

136

values[0x0]

all_enables

biggest_size

73406

1

T1

19

T2

1388

T3

218

values[0x1]

all_enables

biggest_size

53965

1

T1

24

T2

1384

T3

252