Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27756	1			T1	10		T2	6		T3	4
auto[PWRUP]	119	1			T11	1		T16	1		T33	3
auto[ONEST_0]	54	1			T11	1		T33	1		T78	1
auto[ONEST_021]	7	1			T165	2		T166	1		T167	1
auto[ONEST_1]	62	1			T11	2		T33	2		T78	1
auto[ONEST_DONE]	7	1			T168	1		T169	1		T170	1
auto[LP_0]	103	1			T11	2		T16	2		T30	2
auto[LP_021]	21	1			T78	2		T95	1		T171	1
auto[LP_1]	129	1			T11	2		T33	2		T78	1
auto[LP_EVAL]	63	1			T11	1		T30	1		T33	1
auto[LP_SLP]	441	1			T11	5		T16	1		T30	2
auto[LP_PWRUP]	30	1			T33	1		T78	2		T112	1
auto[NP_0]	138	1			T11	1		T16	1		T30	1
auto[NP_021]	41	1			T33	1		T112	1		T172	1
auto[NP_1]	135	1			T11	1		T33	2		T78	1
auto[NP_EVAL]	34	1			T78	1		T112	2		T171	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T112

1

T173

1

T174

1

min

27191

1

T1

10

T2

6

T3

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27202	1			T1	10		T2	6		T3	4
pow[0x1]	8	1			T141	1		T175	1		T176	2
pow[0x2]	11	1			T172	1		T177	1		T178	2
pow[0x3]	26	1			T16	1		T33	1		T78	2
pow[0x4]	50	1			T33	2		T78	2		T94	1
pow[0x5]	117	1			T11	2		T33	3		T95	3
pow[0x6]	275	1			T11	2		T16	1		T30	4
pow[0x7]	451	1			T11	4		T16	2		T30	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T11

3

T33

4

T78

7

min

26777

1

T1

10

T2

6

T3

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26777	1			T1	10		T2	6		T3	4
pow[0x6]	2	1			T179	1		T180	1		-	-
pow[0x7]	1	1			T181	1		-	-		-	-
pow[0x8]	4	1			T94	1		T179	1		T182	1
pow[0x9]	10	1			T78	1		T183	1		T184	1
pow[0xa]	14	1			T78	1		T51	1		T185	1
pow[0xb]	32	1			T33	1		T112	1		T186	1
pow[0xc]	71	1			T33	1		T78	5		T95	1
pow[0xd]	116	1			T33	3		T78	1		T95	4
pow[0xe]	271	1			T11	1		T16	2		T30	1
pow[0xf]	530	1			T11	6		T16	3		T30	3