Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2278	1			T3	20		T4	10		T32	2
auto[PWRUP]	146	1			T11	6		T16	1		T78	3
auto[ONEST_0]	85	1			T11	1		T30	1		T33	5
auto[ONEST_021]	14	1			T11	2		T95	1		T112	1
auto[ONEST_1]	92	1			T30	1		T33	2		T78	2
auto[ONEST_DONE]	8	1			T78	1		T177	1		T165	1
auto[LP_0]	118	1			T11	1		T33	2		T78	2
auto[LP_021]	33	1			T30	1		T33	2		T78	1
auto[LP_1]	119	1			T11	2		T30	1		T33	1
auto[LP_EVAL]	61	1			T16	1		T33	2		T94	1
auto[LP_SLP]	522	1			T11	10		T12	2		T16	3
auto[LP_PWRUP]	28	1			T78	1		T95	1		T139	1
auto[NP_0]	211	1			T11	2		T12	2		T16	1
auto[NP_021]	45	1			T16	1		T30	1		T33	4
auto[NP_1]	208	1			T12	2		T16	1		T30	4
auto[NP_EVAL]	35	1			T30	3		T33	1		T78	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T11

1

T33

1

T139

1

min

1918

1

T3

20

T4

10

T32

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1928	1			T3	20		T4	10		T32	2
pow[0x1]	15	1			T11	1		T12	1		T94	1
pow[0x2]	14	1			T78	1		T141	1		T173	1
pow[0x3]	25	1			T11	1		T16	1		T78	1
pow[0x4]	72	1			T16	1		T30	1		T78	2
pow[0x5]	120	1			T30	1		T33	1		T78	2
pow[0x6]	256	1			T11	9		T16	1		T33	4
pow[0x7]	530	1			T11	10		T16	2		T30	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

205

1

T11

4

T33

5

T78

1

min

1311

1

T3

20

T4

10

T32

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1318	1			T3	20		T4	10		T32	2
pow[0x1]	27	1			T94	3		T114	2		T88	6
pow[0x2]	21	1			T30	6		T78	1		T95	1
pow[0x3]	43	1			T16	1		T95	3		T139	1
pow[0x4]	56	1			T12	4		T16	2		T78	2
pow[0x6]	4	1			T177	1		T167	2		T180	1
pow[0x7]	1	1			T179	1		-	-		-	-
pow[0x8]	2	1			T175	1		T321	1		-	-
pow[0x9]	11	1			T33	1		T141	1		T322	1
pow[0xa]	13	1			T30	1		T33	1		T112	1
pow[0xb]	33	1			T11	1		T30	1		T33	1
pow[0xc]	67	1			T11	2		T30	1		T33	1
pow[0xd]	143	1			T11	4		T33	3		T94	1
pow[0xe]	299	1			T11	4		T16	1		T30	1
pow[0xf]	595	1			T11	11		T16	3		T30	2