Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	96.84		100.00	92.77	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmStateHwReset_A	1174	1174	0	0
FsmStateSwReset_A	28907607	6410	0	0
LpSampleCntHwReset_A	1174	1174	0	0
LpSampleCntSwReset_A	28907607	6410	0	0
NpSampleCntHwReset_A	1174	1174	0	0
NpSampleCntSwReset_A	28907607	6410	0	0
PwrupTimerCntHwReset_A	1174	1174	0	0
PwrupTimerCntSwReset_A	28907607	6410	0	0
WakeupTimerCntHwReset_A	1174	1174	0	0
WakeupTimerCntSwReset_A	28907607	6410	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1174	1174	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	8	8	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	7	7	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28907607	6410	0	0
T10	65374	16	0	0
T11	84	0	0	0
T12	3402	0	0	0
T13	32766	5	0	0
T14	97730	24	0	0
T15	32696	7	0	0
T16	8947	0	0	0
T17	66960	16	0	0
T18	940	0	0	0
T19	32556	7	0	0
T20	0	22	0	0
T21	0	6	0	0
T53	0	23	0	0
T54	0	5	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1174	1174	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	8	8	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	7	7	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28907607	6410	0	0
T10	65374	16	0	0
T11	84	0	0	0
T12	3402	0	0	0
T13	32766	5	0	0
T14	97730	24	0	0
T15	32696	7	0	0
T16	8947	0	0	0
T17	66960	16	0	0
T18	940	0	0	0
T19	32556	7	0	0
T20	0	22	0	0
T21	0	6	0	0
T53	0	23	0	0
T54	0	5	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1174	1174	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	8	8	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	7	7	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28907607	6410	0	0
T10	65374	16	0	0
T11	84	0	0	0
T12	3402	0	0	0
T13	32766	5	0	0
T14	97730	24	0	0
T15	32696	7	0	0
T16	8947	0	0	0
T17	66960	16	0	0
T18	940	0	0	0
T19	32556	7	0	0
T20	0	22	0	0
T21	0	6	0	0
T53	0	23	0	0
T54	0	5	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1174	1174	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	8	8	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	7	7	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28907607	6410	0	0
T10	65374	16	0	0
T11	84	0	0	0
T12	3402	0	0	0
T13	32766	5	0	0
T14	97730	24	0	0
T15	32696	7	0	0
T16	8947	0	0	0
T17	66960	16	0	0
T18	940	0	0	0
T19	32556	7	0	0
T20	0	22	0	0
T21	0	6	0	0
T53	0	23	0	0
T54	0	5	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1174	1174	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	8	8	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	7	7	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28907607	6410	0	0
T10	65374	16	0	0
T11	84	0	0	0
T12	3402	0	0	0
T13	32766	5	0	0
T14	97730	24	0	0
T15	32696	7	0	0
T16	8947	0	0	0
T17	66960	16	0	0
T18	940	0	0	0
T19	32556	7	0	0
T20	0	22	0	0
T21	0	6	0	0
T53	0	23	0	0
T54	0	5	0	0