Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T11,T16,T18

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T15
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T16
1	0	Covered	T11,T12,T14
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T17
1	0	Covered	T10,T13,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T12,T13

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T16
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T11,T12,T13
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T17,T20
0	1	Covered	T10,T17,T20
1	0	Covered	T10,T12,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
1	0	Covered	T10,T15,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T16
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T20
0	1	Covered	T10,T13,T20
1	0	Covered	T10,T13,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
1	0	Covered	T15,T16,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T16,T17
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T16,T17
0	1	Covered	T10,T17,T20
1	0	Covered	T10,T16,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T16
1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T17
0	1	Covered	T10,T14,T19
1	0	Covered	T10,T14,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T16
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T11,T12,T14
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T17
0	1	Covered	T10,T13,T17
1	0	Covered	T10,T13,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T15
0	1	Covered	T10,T13,T15
1	0	Covered	T10,T12,T13

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T17
0	1	Covered	T10,T13,T17
1	0	Covered	T10,T12,T13

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
1	0	Covered	T10,T15,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T10,T13,T16
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T20
0	1	Covered	T10,T13,T20
1	0	Covered	T10,T13,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
1	0	Covered	T10,T15,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T16,T17
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T16,T17
0	1	Covered	T10,T17,T20
1	0	Covered	T10,T16,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T10,T14,T16
1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T17
0	1	Covered	T10,T14,T17
1	0	Covered	T10,T14,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T13,T14,T16
1	1	0	Covered	T13,T14,T17
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T14,T17
1	1	0	Covered	T14,T19,T20
1	1	1	Covered	T10,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T17
0	1	Covered	T10,T14,T17
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T20
1	0	Covered	T10,T11,T12
1	1	Covered	T14,T19,T20

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T14,T17
1	1	0	Covered	T13,T14,T17
1	1	1	Covered	T10,T12,T13

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T17
0	1	Covered	T10,T12,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T12,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T13,T14
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T12,T14,T19
1	1	0	Covered	T14,T19,T20
1	1	1	Covered	T12,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T19
0	1	Covered	T12,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T19
1	0	Covered	T10,T11,T12
1	1	Covered	T12,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T19
0	1	Covered	T12,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T19
1	0	Covered	T10,T11,T12
1	1	Covered	T12,T14,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T13,T14,T17
1	1	0	Covered	T13,T14,T17
1	1	1	Covered	T13,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T13,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T17
1	0	Covered	T10,T11,T12
1	1	Covered	T13,T14,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T11,T12
1	1	Covered	T12,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T11,T12
1	0	1	Covered	T10,T14,T16
1	1	0	Covered	T10,T14,T16
1	1	1	Covered	T10,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T16
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T16
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T14,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T10,T12,T13
1	1	Covered	T13,T14,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T17
1	0	Covered	T10,T12,T13
1	1	Covered	T10,T14,T17

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T12,T13

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T12,T13
1	1	Covered	T10,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T16
1	0	Covered	T10,T12,T13
1	1	Covered	T12,T14,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T16
1	0	Covered	T10,T12,T13
1	1	Covered	T13,T14,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T10,T12,T13
1	1	Covered	T12,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T16
1	0	Covered	T10,T12,T13
1	1	Covered	T10,T14,T16

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T16,T18
0	1	Covered	T10,T11,T12
0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T12,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T13,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T16,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T16,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T14,T16

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31312020	31001439	0	0
gen_filter_match[0].MatchCheck00_A	31312020	9469485	0	0
gen_filter_match[0].MatchCheck01_A	31312020	2619919	0	0
gen_filter_match[0].MatchCheck10_A	31312020	2436206	0	0
gen_filter_match[0].MatchCheck11_A	31312020	16475829	0	0
gen_filter_match[1].MatchCheck00_A	31312020	10739149	0	0
gen_filter_match[1].MatchCheck01_A	31312020	1093525	0	0
gen_filter_match[1].MatchCheck10_A	31312020	1047227	0	0
gen_filter_match[1].MatchCheck11_A	31312020	18121538	0	0
gen_filter_match[2].MatchCheck00_A	31312020	10696855	0	0
gen_filter_match[2].MatchCheck01_A	31312020	536206	0	0
gen_filter_match[2].MatchCheck10_A	31312020	664989	0	0
gen_filter_match[2].MatchCheck11_A	31312020	19103389	0	0
gen_filter_match[3].MatchCheck00_A	31312020	11554680	0	0
gen_filter_match[3].MatchCheck01_A	31312020	328880	0	0
gen_filter_match[3].MatchCheck10_A	31312020	163768	0	0
gen_filter_match[3].MatchCheck11_A	31312020	18954111	0	0
gen_filter_match[4].MatchCheck00_A	31312020	11698592	0	0
gen_filter_match[4].MatchCheck01_A	31312020	32951	0	0
gen_filter_match[4].MatchCheck10_A	31312020	112	0	0
gen_filter_match[4].MatchCheck11_A	31312020	19269784	0	0
gen_filter_match[5].MatchCheck00_A	31312020	11870006	0	0
gen_filter_match[5].MatchCheck01_A	31312020	32085	0	0
gen_filter_match[5].MatchCheck10_A	31312020	98785	0	0
gen_filter_match[5].MatchCheck11_A	31312020	19000563	0	0
gen_filter_match[6].MatchCheck00_A	31312020	12139657	0	0
gen_filter_match[6].MatchCheck01_A	31312020	16	0	0
gen_filter_match[6].MatchCheck10_A	31312020	32425	0	0
gen_filter_match[6].MatchCheck11_A	31312020	18829341	0	0
gen_filter_match[7].MatchCheck00_A	31312020	11249900	0	0
gen_filter_match[7].MatchCheck01_A	31312020	103340	0	0
gen_filter_match[7].MatchCheck10_A	31312020	66132	0	0
gen_filter_match[7].MatchCheck11_A	31312020	19582067	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	31001439	0	0
T10	65374	65275	0	0
T11	21074	17649	0	0
T12	6209	5392	0	0
T13	32766	32688	0	0
T14	97730	97676	0	0
T15	32696	32607	0	0
T16	20064	18729	0	0
T17	66960	66885	0	0
T18	940	867	0	0
T19	32556	32495	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	9469485	0	0
T10	65374	65275	0	0
T11	21074	17475	0	0
T12	6209	122	0	0
T13	32766	4	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	14846	0	0
T17	66960	33740	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	2619919	0	0
T17	66960	33145	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	31819	0	0
T21	33373	0	0	0
T46	0	32162	0	0
T53	98524	0	0	0
T54	34012	0	0	0
T79	1167	0	0	0
T80	1144	0	0	0
T84	0	32940	0	0
T85	0	31022	0	0
T86	0	34650	0	0
T87	0	32713	0	0
T88	0	906	0	0
T89	0	33847	0	0
T90	0	32679	0	0
T91	65411	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	2436206	0	0
T55	97899	32743	0	0
T81	33338	0	0	0
T82	1214	0	0	0
T84	96626	31338	0	0
T92	98872	1	0	0
T93	32568	2	0	0
T94	0	1	0	0
T95	0	32699	0	0
T96	0	32649	0	0
T97	0	32350	0	0
T98	0	32641	0	0
T99	0	1	0	0
T100	32793	0	0	0
T101	32236	0	0	0
T102	32161	0	0	0
T103	66112	0	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	16475829	0	0
T11	21074	174	0	0
T12	6209	5270	0	0
T13	32766	32684	0	0
T14	97730	97672	0	0
T15	32696	0	0	0
T16	20064	3883	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	65335	0	0
T21	0	33290	0	0
T53	0	98461	0	0
T54	0	33919	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	10739149	0	0
T10	65374	32198	0	0
T11	21074	17649	0	0
T12	6209	5392	0	0
T13	32766	32688	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	18729	0	0
T17	66960	33148	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	1093525	0	0
T30	66339	21234	0	0
T33	71120	0	0	0
T78	35669	9193	0	0
T83	743	0	0	0
T84	96626	32283	0	0
T85	97992	0	0	0
T94	17821	0	0	0
T95	88052	0	0	0
T104	0	32312	0	0
T105	0	1	0	0
T106	0	32572	0	0
T107	0	33065	0	0
T108	0	32614	0	0
T109	0	33273	0	0
T110	0	65145	0	0
T111	65106	0	0	0
T112	56322	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	1047227	0	0
T10	65374	33077	0	0
T11	21074	0	0	0
T12	6209	0	0	0
T13	32766	0	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	0	0	0
T17	66960	33737	0	0
T18	940	0	0	0
T19	32556	0	0	0
T30	0	34013	0	0
T92	0	1	0	0
T93	0	2	0	0
T99	0	1	0	0
T113	0	32332	0	0
T114	0	3647	0	0
T115	0	34575	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	18121538	0	0
T14	97730	97671	0	0
T15	32696	0	0	0
T16	20064	0	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	31819	0	0
T21	33373	33290	0	0
T53	98524	98461	0	0
T54	0	33919	0	0
T79	1167	0	0	0
T84	0	31338	0	0
T91	0	65346	0	0
T92	0	98816	0	0
T116	0	64146	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	10696855	0	0
T10	65374	33080	0	0
T11	21074	17649	0	0
T12	6209	122	0	0
T13	32766	4	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	10212	0	0
T17	66960	3	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	536206	0	0
T13	32766	32684	0	0
T14	97730	0	0	0
T15	32696	0	0	0
T16	20064	0	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	32697	0	0
T21	33373	33290	0	0
T79	1167	0	0	0
T89	0	33530	0	0
T100	0	32718	0	0
T113	0	32014	0	0
T117	0	14194	0	0
T118	0	32960	0	0
T119	0	1	0	0
T120	0	32988	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	664989	0	0
T10	65374	32195	0	0
T11	21074	0	0	0
T12	6209	0	0	0
T13	32766	0	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	2	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T50	0	33313	0	0
T92	0	1	0	0
T93	0	2	0	0
T99	0	1	0	0
T103	0	1	0	0
T121	0	32628	0	0
T122	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	19103389	0	0
T12	6209	5270	0	0
T13	32766	0	0	0
T14	97730	97671	0	0
T15	32696	0	0	0
T16	20064	8515	0	0
T17	66960	66882	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	0	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T79	1167	0	0	0
T91	0	65346	0	0
T92	0	98816	0	0
T116	0	64146	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	11554680	0	0
T10	65374	33080	0	0
T11	21074	17649	0	0
T12	6209	5392	0	0
T13	32766	4	0	0
T14	97730	4	0	0
T15	32696	3	0	0
T16	20064	18729	0	0
T17	66960	66885	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	328880	0	0
T105	0	1	0	0
T108	0	1	0	0
T123	99527	34274	0	0
T124	33493	32201	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	33181	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	2	0	0
T131	98037	0	0	0
T132	66279	0	0	0
T133	66564	0	0	0
T134	32125	0	0	0
T135	6205	0	0	0
T136	21146	0	0	0
T137	1185	0	0	0
T138	1160	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	163768	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	0	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	0	0	0
T21	33373	0	0	0
T53	98524	0	0	0
T79	1167	0	0	0
T92	0	1	0	0
T99	0	1	0	0
T105	0	1	0	0
T119	0	1	0	0
T122	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	18954111	0	0
T10	65374	32195	0	0
T11	21074	0	0	0
T12	6209	0	0	0
T13	32766	32684	0	0
T14	97730	97671	0	0
T15	32696	32604	0	0
T16	20064	0	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	0	32697	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T91	0	65346	0	0
T116	0	64146	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	11698592	0	0
T10	65374	65275	0	0
T11	21074	17649	0	0
T12	6209	122	0	0
T13	32766	32688	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	7149	0	0
T17	66960	66885	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	32951	0	0
T30	66339	0	0	0
T33	71120	0	0	0
T78	35669	0	0	0
T83	743	0	0	0
T85	97992	1	0	0
T94	17821	0	0	0
T95	88052	0	0	0
T99	0	1	0	0
T105	0	1	0	0
T108	0	1	0	0
T111	65106	0	0	0
T113	96804	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	32941	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	73390	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	112	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	3	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	0	0	0
T21	33373	0	0	0
T53	98524	0	0	0
T79	1167	0	0	0
T85	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	4	0	0
T99	0	1	0	0
T103	0	1	0	0
T139	0	3	0	0
T149	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	19269784	0	0
T12	6209	5270	0	0
T13	32766	0	0	0
T14	97730	97671	0	0
T15	32696	0	0	0
T16	20064	11577	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	31819	0	0
T21	0	33290	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T79	1167	0	0	0
T91	0	65346	0	0
T116	0	64146	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	11870006	0	0
T10	65374	65275	0	0
T11	21074	17649	0	0
T12	6209	5392	0	0
T13	32766	4	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	15666	0	0
T17	66960	33740	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	32085	0	0
T30	66339	0	0	0
T33	71120	0	0	0
T78	35669	0	0	0
T83	743	0	0	0
T85	97992	0	0	0
T94	17821	0	0	0
T99	0	1	0	0
T103	66112	1	0	0
T109	0	1	0	0
T111	65106	0	0	0
T113	96804	1	0	0
T123	0	32068	0	0
T129	0	1	0	0
T148	73390	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	98785	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	1	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	0	0	0
T21	33373	0	0	0
T53	98524	0	0	0
T79	1167	0	0	0
T92	0	1	0	0
T93	0	2	0	0
T99	0	1	0	0
T103	0	1	0	0
T113	0	1	0	0
T140	0	1	0	0
T149	0	1	0	0
T154	0	3	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	19000563	0	0
T13	32766	32684	0	0
T14	97730	97671	0	0
T15	32696	0	0	0
T16	20064	3062	0	0
T17	66960	33145	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	97154	0	0
T21	33373	0	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T79	1167	0	0	0
T91	0	65346	0	0
T116	0	64146	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	12139657	0	0
T10	65374	65275	0	0
T11	21074	17649	0	0
T12	6209	122	0	0
T13	32766	4	0	0
T14	97730	4	0	0
T15	32696	3	0	0
T16	20064	7149	0	0
T17	66960	66885	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	16	0	0
T30	66339	0	0	0
T33	71120	0	0	0
T78	35669	0	0	0
T83	743	0	0	0
T85	97992	1	0	0
T94	17821	0	0	0
T95	88052	0	0	0
T99	0	1	0	0
T108	0	1	0	0
T110	0	1	0	0
T111	65106	0	0	0
T113	96804	1	0	0
T125	0	1	0	0
T143	0	1	0	0
T148	73390	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	32425	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	3	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	0	0	0
T21	33373	0	0	0
T53	98524	0	0	0
T79	1167	0	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	4	0	0
T99	0	1	0	0
T103	0	1	0	0
T113	0	2	0	0
T139	0	4	0	0
T149	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	18829341	0	0
T12	6209	5270	0	0
T13	32766	32684	0	0
T14	97730	97671	0	0
T15	32696	32604	0	0
T16	20064	11577	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	97213	31819	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T79	1167	0	0	0
T91	0	65346	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	11249900	0	0
T10	65374	3	0	0
T11	21074	17649	0	0
T12	6209	5392	0	0
T13	32766	32688	0	0
T14	97730	4	0	0
T15	32696	32607	0	0
T16	20064	7149	0	0
T17	66960	33740	0	0
T18	940	867	0	0
T19	32556	4	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	103340	0	0
T30	66339	0	0	0
T33	71120	0	0	0
T78	35669	0	0	0
T83	743	0	0	0
T85	97992	0	0	0
T94	17821	0	0	0
T95	88052	0	0	0
T96	0	32084	0	0
T105	0	1	0	0
T108	0	1	0	0
T111	65106	0	0	0
T113	96804	1	0	0
T143	0	1	0	0
T148	73390	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	66132	0	0
T14	97730	1	0	0
T15	32696	0	0	0
T16	20064	3	0	0
T17	66960	0	0	0
T18	940	0	0	0
T19	32556	0	0	0
T20	97213	0	0	0
T21	33373	0	0	0
T53	98524	0	0	0
T79	1167	0	0	0
T93	0	3	0	0
T99	0	1	0	0
T103	0	1	0	0
T113	0	1	0	0
T122	0	1	0	0
T139	0	5	0	0
T140	0	1	0	0
T149	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31312020	19582067	0	0
T10	65374	65272	0	0
T11	21074	0	0	0
T12	6209	0	0	0
T13	32766	0	0	0
T14	97730	97671	0	0
T15	32696	0	0	0
T16	20064	11577	0	0
T17	66960	33145	0	0
T18	940	0	0	0
T19	32556	32491	0	0
T20	0	65335	0	0
T53	0	98461	0	0
T54	0	33919	0	0
T91	0	65346	0	0
T116	0	64146	0	0