Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6503	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2068	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2330	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2211	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2206	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2128	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2202	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2130	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2290	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2217	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2241	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2079	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2202	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2165	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2171	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2050	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2139	0	0
adc_en_ctl_rd_A	2147483647	1588	0	0
adc_fsm_rst_rd_A	2147483647	1494	0	0
adc_intr_ctl_rd_A	2147483647	1520	0	0
adc_lp_sample_ctl_rd_A	2147483647	1465	0	0
adc_pd_ctl_rd_A	2147483647	1983	0	0
adc_sample_ctl_rd_A	2147483647	1567	0	0
adc_wakeup_ctl_rd_A	2147483647	1382	0	0
intr_enable_rd_A	2147483647	1837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6503	0	0
T3	748099	2	0	0
T4	108984	0	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	0	0	0
T22	42979	0	0	0
T23	17984	253	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T34	39898	234	0	0
T35	0	201	0	0
T56	0	281	0	0
T57	0	248	0	0
T58	0	361	0	0
T59	0	590	0	0
T60	0	471	0	0
T76	0	727	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T4	108984	37	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	80	0	0
T22	42979	0	0	0
T23	17984	9	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	22	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T35	0	6	0	0
T62	0	30	0	0
T65	0	110	0	0
T74	0	38	0	0
T161	0	5	0	0
T162	0	6	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2330	0	0
T4	108984	37	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	99	0	0
T22	42979	0	0	0
T23	17984	22	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	6	0	0
T34	39898	0	0	0
T35	0	8	0	0
T62	0	24	0	0
T65	0	114	0	0
T74	0	27	0	0
T161	0	4	0	0
T163	0	14	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2211	0	0
T4	108984	76	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	112	0	0
T22	42979	0	0	0
T23	17984	12	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	5	0	0
T31	29983	0	0	0
T32	0	4	0	0
T34	39898	0	0	0
T62	0	19	0	0
T65	0	113	0	0
T66	0	92	0	0
T74	0	57	0	0
T163	0	19	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2206	0	0
T4	108984	51	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	131	0	0
T22	42979	0	0	0
T23	17984	51	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	8	0	0
T31	29983	0	0	0
T32	0	5	0	0
T34	39898	0	0	0
T35	0	11	0	0
T62	0	12	0	0
T74	0	57	0	0
T161	0	4	0	0
T162	0	5	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T4	108984	60	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	104	0	0
T22	42979	0	0	0
T23	17984	7	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	13	0	0
T31	29983	0	0	0
T32	0	1	0	0
T34	39898	0	0	0
T62	0	52	0	0
T65	0	129	0	0
T74	0	34	0	0
T161	0	8	0	0
T163	0	40	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T4	108984	43	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	104	0	0
T22	42979	0	0	0
T23	17984	1	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	5	0	0
T34	39898	0	0	0
T35	0	8	0	0
T62	0	10	0	0
T65	0	114	0	0
T74	0	55	0	0
T161	0	1	0	0
T163	0	23	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2130	0	0
T4	108984	59	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	96	0	0
T22	42979	0	0	0
T23	17984	42	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	1	0	0
T34	39898	0	0	0
T35	0	4	0	0
T62	0	22	0	0
T65	0	125	0	0
T74	0	42	0	0
T161	0	2	0	0
T163	0	8	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2290	0	0
T4	108984	54	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	104	0	0
T22	42979	0	0	0
T23	17984	11	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	6	0	0
T34	39898	0	0	0
T35	0	9	0	0
T62	0	20	0	0
T65	0	130	0	0
T66	0	103	0	0
T74	0	61	0	0
T163	0	32	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2217	0	0
T4	108984	63	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	140	0	0
T22	42979	0	0	0
T23	17984	24	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	14	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T35	0	20	0	0
T62	0	19	0	0
T65	0	115	0	0
T74	0	24	0	0
T161	0	2	0	0
T163	0	24	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2241	0	0
T4	108984	42	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	102	0	0
T22	42979	0	0	0
T23	17984	46	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	3	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T62	0	5	0	0
T65	0	100	0	0
T66	0	115	0	0
T74	0	28	0	0
T162	0	1	0	0
T163	0	10	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2079	0	0
T4	108984	47	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	137	0	0
T22	42979	0	0	0
T23	17984	25	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	8	0	0
T34	39898	0	0	0
T35	0	9	0	0
T62	0	20	0	0
T65	0	90	0	0
T74	0	35	0	0
T161	0	8	0	0
T163	0	40	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T4	108984	71	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	99	0	0
T22	42979	0	0	0
T23	17984	0	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	23	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T35	0	26	0	0
T62	0	31	0	0
T65	0	105	0	0
T66	0	93	0	0
T74	0	58	0	0
T161	0	6	0	0
T163	0	8	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2165	0	0
T4	108984	79	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	79	0	0
T22	42979	0	0	0
T23	17984	8	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	3	0	0
T31	29983	0	0	0
T32	0	3	0	0
T34	39898	0	0	0
T35	0	17	0	0
T62	0	6	0	0
T65	0	92	0	0
T74	0	50	0	0
T161	0	9	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T4	108984	21	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	123	0	0
T22	42979	0	0	0
T23	17984	26	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	22	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T35	0	11	0	0
T62	0	20	0	0
T65	0	127	0	0
T66	0	86	0	0
T74	0	21	0	0
T163	0	32	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2050	0	0
T4	108984	52	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	130	0	0
T22	42979	0	0	0
T23	17984	12	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	17	0	0
T31	29983	0	0	0
T32	0	8	0	0
T34	39898	0	0	0
T35	0	9	0	0
T62	0	1	0	0
T65	0	87	0	0
T74	0	32	0	0
T161	0	2	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2139	0	0
T4	108984	51	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	121	0	0
T22	42979	0	0	0
T23	17984	20	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	14	0	0
T31	29983	0	0	0
T32	0	4	0	0
T34	39898	0	0	0
T35	0	11	0	0
T62	0	20	0	0
T65	0	118	0	0
T74	0	9	0	0
T161	0	1	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T4	108984	16	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	92	0	0
T22	42979	0	0	0
T23	17984	23	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T34	39898	0	0	0
T35	0	6	0	0
T62	0	16	0	0
T65	0	134	0	0
T74	0	17	0	0
T161	0	1	0	0
T162	0	7	0	0
T163	0	35	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1494	0	0
T4	108984	30	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	122	0	0
T22	42979	0	0	0
T23	17984	8	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	6	0	0
T31	29983	0	0	0
T32	0	3	0	0
T34	39898	0	0	0
T35	0	19	0	0
T62	0	12	0	0
T74	0	32	0	0
T161	0	2	0	0
T162	0	8	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1520	0	0
T4	108984	14	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	122	0	0
T22	42979	0	0	0
T23	17984	24	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	1	0	0
T31	29983	0	0	0
T32	0	1	0	0
T34	39898	0	0	0
T35	0	21	0	0
T62	0	11	0	0
T65	0	150	0	0
T74	0	22	0	0
T161	0	9	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1465	0	0
T4	108984	17	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	142	0	0
T22	42979	0	0	0
T23	17984	16	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	6	0	0
T34	39898	0	0	0
T35	0	2	0	0
T62	0	3	0	0
T65	0	127	0	0
T74	0	55	0	0
T161	0	1	0	0
T162	0	7	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1983	0	0
T4	108984	44	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	112	0	0
T22	42979	0	0	0
T23	17984	21	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	2	0	0
T31	29983	0	0	0
T32	0	4	0	0
T34	39898	0	0	0
T35	0	18	0	0
T62	0	25	0	0
T65	0	103	0	0
T74	0	13	0	0
T161	0	5	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1567	0	0
T4	108984	10	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	140	0	0
T22	42979	0	0	0
T23	17984	28	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T31	29983	0	0	0
T32	0	6	0	0
T34	39898	0	0	0
T35	0	10	0	0
T62	0	12	0	0
T65	0	110	0	0
T66	0	100	0	0
T74	0	65	0	0
T163	0	37	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1382	0	0
T4	108984	7	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	98	0	0
T22	42979	0	0	0
T23	17984	23	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	2	0	0
T31	29983	0	0	0
T32	0	10	0	0
T34	39898	0	0	0
T35	0	2	0	0
T62	0	13	0	0
T74	0	52	0	0
T161	0	18	0	0
T162	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T4	108984	12	0	0
T5	55530	0	0	0
T6	11484	0	0	0
T7	101440	141	0	0
T22	42979	0	0	0
T23	17984	28	0	0
T24	11300	0	0	0
T25	23262	0	0	0
T26	0	7	0	0
T31	29983	0	0	0
T32	0	2	0	0
T34	39898	0	0	0
T35	0	18	0	0
T61	0	6	0	0
T74	0	2	0	0
T161	0	1	0	0
T164	0	29	0	0