Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1218422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1175990

1

T1

56

T2

456

T3

2160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2092631	1			T1	82		T2	832		T3	4173
values[0x0]	150285	1			T1	30		T2	47		T3	161
values[0x1]	151496	1			T1	34		T2	46		T3	166

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	980663	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1413749

1

T1

70

T2

554

T3

2606

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7067	1			T2	3		T3	20		T5	2
valid_sources[0x01]	11291	1			T1	1		T2	4		T3	19
valid_sources[0x02]	11182	1			T2	6		T3	18		T5	5
valid_sources[0x03]	6858	1			T2	7		T3	16		T5	1
valid_sources[0x04]	6487	1			T2	2		T3	21		T5	1
valid_sources[0x05]	11116	1			T1	1		T2	1		T3	14
valid_sources[0x06]	8195	1			T1	1		T3	24		T5	1
valid_sources[0x07]	6728	1			T1	1		T2	6		T3	13
valid_sources[0x08]	7281	1			T2	2		T3	13		T5	14
valid_sources[0x09]	20944	1			T2	4		T3	22		T5	4
valid_sources[0x0a]	7359	1			T2	4		T3	17		T5	3
valid_sources[0x0b]	6978	1			T1	1		T2	9		T3	15
valid_sources[0x0c]	15274	1			T2	3		T3	19		T5	10
valid_sources[0x0d]	11019	1			T2	9		T3	13		T5	12
valid_sources[0x0e]	12286	1			T1	3		T2	4		T3	22
valid_sources[0x0f]	9744	1			T2	2		T3	13		T5	7
valid_sources[0x10]	6885	1			T1	1		T2	1		T3	17
valid_sources[0x11]	7215	1			T2	2		T3	18		T5	4
valid_sources[0x12]	6907	1			T2	7		T3	16		T5	9
valid_sources[0x13]	6989	1			T2	7		T3	18		T5	1
valid_sources[0x14]	7066	1			T2	2		T3	19		T5	10
valid_sources[0x15]	6880	1			T2	3		T3	14		T5	2
valid_sources[0x16]	12457	1			T2	5		T3	14		T5	17
valid_sources[0x17]	8283	1			T2	5		T3	17		T5	4
valid_sources[0x18]	7510	1			T2	6		T3	13		T5	2
valid_sources[0x19]	7015	1			T2	5		T3	27		T5	2
valid_sources[0x1a]	8400	1			T2	1		T3	24		T5	3
valid_sources[0x1b]	9770	1			T2	5		T3	10		T5	2
valid_sources[0x1c]	8008	1			T1	1		T2	9		T3	14
valid_sources[0x1d]	7792	1			T2	6		T3	12		T5	5
valid_sources[0x1e]	7520	1			T2	1		T3	17		T5	1
valid_sources[0x1f]	8562	1			T2	4		T3	6		T5	8
valid_sources[0x20]	7673	1			T2	2		T3	16		T5	11
valid_sources[0x21]	11303	1			T1	2		T2	5		T3	26
valid_sources[0x22]	11400	1			T2	8		T3	20		T5	4
valid_sources[0x23]	13354	1			T2	3		T3	26		T5	7
valid_sources[0x24]	6809	1			T1	2		T2	1		T3	20
valid_sources[0x25]	6903	1			T1	1		T2	7		T3	12
valid_sources[0x26]	7123	1			T1	1		T3	23		T5	10
valid_sources[0x27]	11191	1			T1	2		T2	5		T3	20
valid_sources[0x28]	11720	1			T2	4		T3	17		T5	7
valid_sources[0x29]	8674	1			T2	8		T3	19		T5	11
valid_sources[0x2a]	7286	1			T2	5		T3	22		T5	12
valid_sources[0x2b]	7861	1			T2	2		T3	14		T5	6
valid_sources[0x2c]	6934	1			T1	1		T2	2		T3	16
valid_sources[0x2d]	7298	1			T2	1		T3	16		T5	9
valid_sources[0x2e]	11269	1			T2	2		T3	15		T5	1
valid_sources[0x2f]	7027	1			T2	2		T3	24		T5	7
valid_sources[0x30]	9376	1			T2	4		T3	10		T5	6
valid_sources[0x31]	7344	1			T2	6		T3	15		T5	8
valid_sources[0x32]	16542	1			T2	1		T3	14		T5	7
valid_sources[0x33]	11412	1			T2	3		T3	16		T5	10
valid_sources[0x34]	8669	1			T2	4		T3	13		T8	52
valid_sources[0x35]	7240	1			T2	3		T3	17		T5	1
valid_sources[0x36]	9059	1			T1	1		T2	4		T3	23
valid_sources[0x37]	7100	1			T2	8		T3	14		T5	7
valid_sources[0x38]	7207	1			T2	10		T3	15		T5	1
valid_sources[0x39]	19922	1			T2	2		T3	18		T5	1
valid_sources[0x3a]	7797	1			T1	1		T2	4		T3	23
valid_sources[0x3b]	6528	1			T1	3		T2	2		T3	14
valid_sources[0x3c]	8110	1			T1	3		T2	4		T3	26
valid_sources[0x3d]	10835	1			T1	1		T2	1		T3	23
valid_sources[0x3e]	8217	1			T1	2		T2	4		T3	24
valid_sources[0x3f]	12686	1			T1	1		T2	5		T3	20
valid_sources[0x40]	15311	1			T1	1		T2	6		T3	12
valid_sources[0x41]	11334	1			T1	1		T2	5		T3	17
valid_sources[0x42]	7356	1			T2	5		T3	11		T5	3
valid_sources[0x43]	7615	1			T2	1		T3	8		T5	12
valid_sources[0x44]	9706	1			T2	9		T3	22		T5	4
valid_sources[0x45]	9010	1			T1	1		T2	4		T3	21
valid_sources[0x46]	7065	1			T2	11		T3	19		T5	5
valid_sources[0x47]	11213	1			T2	2		T3	11		T5	3
valid_sources[0x48]	15996	1			T2	1		T3	17		T5	7
valid_sources[0x49]	7295	1			T2	4		T3	28		T8	19
valid_sources[0x4a]	7428	1			T2	2		T3	16		T5	3
valid_sources[0x4b]	9665	1			T1	1		T2	2		T3	21
valid_sources[0x4c]	7324	1			T1	2		T2	5		T3	22
valid_sources[0x4d]	7728	1			T2	3		T3	13		T5	9
valid_sources[0x4e]	14652	1			T2	1		T3	15		T8	39
valid_sources[0x4f]	7232	1			T1	1		T2	2		T3	20
valid_sources[0x50]	7071	1			T2	6		T3	18		T5	5
valid_sources[0x51]	7675	1			T2	5		T3	23		T5	5
valid_sources[0x52]	6889	1			T2	2		T3	15		T5	6
valid_sources[0x53]	10057	1			T1	1		T2	4		T3	19
valid_sources[0x54]	7127	1			T2	8		T3	17		T5	2
valid_sources[0x55]	9818	1			T1	1		T3	12		T5	3
valid_sources[0x56]	6769	1			T2	6		T3	19		T5	3
valid_sources[0x57]	6606	1			T1	1		T2	3		T3	27
valid_sources[0x58]	12035	1			T1	2		T2	1		T3	26
valid_sources[0x59]	7251	1			T1	1		T2	8		T3	23
valid_sources[0x5a]	13439	1			T2	5		T3	24		T6	1
valid_sources[0x5b]	11855	1			T3	21		T5	11		T8	24
valid_sources[0x5c]	7643	1			T2	2		T3	19		T5	2
valid_sources[0x5d]	11213	1			T1	1		T2	2		T3	23
valid_sources[0x5e]	7288	1			T2	5		T3	21		T5	1
valid_sources[0x5f]	7752	1			T1	4		T2	5		T3	17
valid_sources[0x60]	8356	1			T1	1		T2	2		T3	22
valid_sources[0x61]	7759	1			T2	11		T3	15		T5	5
valid_sources[0x62]	11314	1			T2	8		T3	23		T5	6
valid_sources[0x63]	7001	1			T2	4		T3	13		T5	6
valid_sources[0x64]	6922	1			T3	25		T5	4		T8	39
valid_sources[0x65]	10923	1			T1	2		T2	4		T3	11
valid_sources[0x66]	6874	1			T2	5		T3	4		T5	2
valid_sources[0x67]	9871	1			T2	1		T3	18		T5	4
valid_sources[0x68]	16642	1			T2	5		T3	21		T5	15
valid_sources[0x69]	13336	1			T1	1		T2	5		T3	17
valid_sources[0x6a]	8755	1			T2	2		T3	18		T5	6
valid_sources[0x6b]	7176	1			T2	3		T3	19		T5	2
valid_sources[0x6c]	6808	1			T2	1		T3	20		T5	1
valid_sources[0x6d]	7174	1			T2	1		T3	20		T5	1
valid_sources[0x6e]	8955	1			T2	4		T3	17		T5	8
valid_sources[0x6f]	8186	1			T1	2		T2	3		T3	27
valid_sources[0x70]	6831	1			T1	1		T2	2		T3	14
valid_sources[0x71]	6917	1			T2	5		T3	23		T8	44
valid_sources[0x72]	6998	1			T2	4		T3	16		T5	2
valid_sources[0x73]	6673	1			T1	1		T3	11		T6	3
valid_sources[0x74]	9895	1			T2	1		T3	13		T5	4
valid_sources[0x75]	6644	1			T1	3		T2	2		T3	19
valid_sources[0x76]	11247	1			T3	18		T5	5		T6	2
valid_sources[0x77]	8196	1			T1	2		T2	6		T3	19
valid_sources[0x78]	11488	1			T2	4		T3	17		T5	7
valid_sources[0x79]	8788	1			T1	2		T2	2		T3	21
valid_sources[0x7a]	8557	1			T2	4		T3	17		T5	4
valid_sources[0x7b]	7315	1			T1	2		T2	4		T3	18
valid_sources[0x7c]	12119	1			T2	1		T3	12		T5	11
valid_sources[0x7d]	7573	1			T2	5		T3	28		T5	1
valid_sources[0x7e]	7859	1			T1	1		T2	3		T3	25
valid_sources[0x7f]	15456	1			T2	5		T3	17		T6	1
valid_sources[0x80]	7071	1			T1	1		T2	2		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1042795

1

T1

42

T2

422

T3

2040

values[0x0]

all_enables

biggest_size

76983

1

T1

9

T2

22

T3

71

values[0x1]

all_enables

biggest_size

56212

1

T1

5

T2

12

T3

49