Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31234	1			T2	6		T3	6		T5	312
auto[PWRUP]	127	1			T5	1		T10	1		T23	2
auto[ONEST_0]	77	1			T5	2		T10	1		T23	1
auto[ONEST_021]	19	1			T5	1		T206	1		T51	1
auto[ONEST_1]	100	1			T5	2		T10	3		T24	4
auto[ONEST_DONE]	5	1			T207	1		T208	1		T209	2
auto[LP_0]	144	1			T5	1		T10	1		T24	1
auto[LP_021]	29	1			T5	2		T10	1		T23	1
auto[LP_1]	156	1			T5	4		T10	1		T23	3
auto[LP_EVAL]	66	1			T23	1		T24	2		T25	1
auto[LP_SLP]	533	1			T5	8		T10	9		T23	6
auto[LP_PWRUP]	22	1			T25	1		T210	1		T51	1
auto[NP_0]	180	1			T5	2		T10	1		T23	2
auto[NP_021]	37	1			T24	1		T155	3		T25	1
auto[NP_1]	161	1			T5	2		T10	2		T23	2
auto[NP_EVAL]	35	1			T10	1		T155	1		T210	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T211

1

T212

1

T213

1

min

30617

1

T2

6

T3

6

T5

306

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30622	1			T2	6		T3	6		T5	306
pow[0x1]	8	1			T155	1		T214	1		T215	2
pow[0x2]	18	1			T23	1		T155	1		T29	1
pow[0x3]	37	1			T206	1		T179	1		T216	1
pow[0x4]	78	1			T5	1		T10	2		T155	3
pow[0x5]	157	1			T5	4		T10	4		T23	2
pow[0x6]	310	1			T5	2		T10	2		T23	5
pow[0x7]	540	1			T5	11		T10	6		T23	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

213

1

T5

3

T10

2

T23

6

min

30125

1

T2

6

T3

6

T5

296

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30125	1			T2	6		T3	6		T5	296
pow[0x2]	1	1			T217	1		-	-		-	-
pow[0x5]	4	1			T218	1		T219	1		T220	1
pow[0x7]	2	1			T221	1		T222	1		-	-
pow[0x8]	4	1			T5	1		T10	1		T24	1
pow[0x9]	7	1			T218	1		T223	1		T220	1
pow[0xa]	18	1			T23	1		T215	1		T224	1
pow[0xb]	43	1			T5	1		T10	1		T24	1
pow[0xc]	75	1			T5	1		T10	1		T23	1
pow[0xd]	163	1			T5	3		T23	4		T24	1
pow[0xe]	300	1			T5	4		T10	1		T23	3
pow[0xf]	673	1			T5	15		T10	10		T23	11