Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2320	1			T3	2		T5	22		T10	11
auto[PWRUP]	150	1			T10	2		T23	3		T24	1
auto[ONEST_0]	96	1			T5	2		T23	2		T155	1
auto[ONEST_021]	22	1			T23	1		T29	1		T214	1
auto[ONEST_1]	103	1			T5	2		T10	1		T23	1
auto[ONEST_DONE]	1	1			T355	1		-	-		-	-
auto[LP_0]	152	1			T5	3		T23	5		T155	3
auto[LP_021]	36	1			T23	2		T155	1		T25	1
auto[LP_1]	147	1			T10	2		T23	1		T24	1
auto[LP_EVAL]	54	1			T10	1		T23	1		T29	1
auto[LP_SLP]	549	1			T5	7		T10	3		T23	9
auto[LP_PWRUP]	29	1			T23	1		T18	1		T214	1
auto[NP_0]	259	1			T5	3		T10	1		T23	4
auto[NP_021]	48	1			T5	2		T10	1		T34	1
auto[NP_1]	244	1			T23	2		T24	3		T155	3
auto[NP_EVAL]	26	1			T155	1		T18	1		T304	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T155

1

T197

1

T356

1

min

1982

1

T3

2

T5

9

T10

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1998	1			T3	2		T5	9		T10	5
pow[0x1]	11	1			T17	1		T126	2		T213	1
pow[0x2]	20	1			T155	1		T25	1		T206	2
pow[0x3]	31	1			T155	1		T25	2		T29	1
pow[0x4]	55	1			T23	1		T17	1		T206	1
pow[0x5]	155	1			T5	3		T10	1		T23	2
pow[0x6]	279	1			T5	7		T10	6		T23	7
pow[0x7]	574	1			T5	6		T10	5		T23	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

218

1

T10

5

T23

2

T155

5

min

1358

1

T3

2

T5

3

T10

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1364	1			T3	2		T5	3		T10	2
pow[0x1]	14	1			T18	1		T236	6		T289	1
pow[0x2]	38	1			T18	2		T195	4		T26	1
pow[0x3]	30	1			T34	1		T17	2		T18	1
pow[0x4]	56	1			T17	1		T18	1		T26	2
pow[0x6]	3	1			T215	1		T357	1		T358	1
pow[0x7]	3	1			T155	1		T224	1		T359	1
pow[0x8]	7	1			T216	1		T215	1		T213	1
pow[0x9]	13	1			T360	1		T213	1		T357	1
pow[0xa]	15	1			T5	1		T23	1		T304	1
pow[0xb]	62	1			T5	1		T155	1		T210	1
pow[0xc]	67	1			T23	1		T24	1		T18	2
pow[0xd]	161	1			T23	4		T155	3		T25	1
pow[0xe]	294	1			T5	7		T10	3		T23	3
pow[0xf]	625	1			T5	10		T10	4		T23	8