Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T14,T16
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T16
0	1	Covered	T3,T14,T16
1	0	Covered	T3,T14,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T8,T16,T20
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T16,T20
0	1	Covered	T8,T16,T20
1	0	Covered	T8,T16,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T8,T16,T123
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T16,T123
0	1	Covered	T8,T16,T123
1	0	Covered	T8,T16,T123

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T11,T16,T20
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T16,T20
0	1	Covered	T16,T20,T123
1	0	Covered	T11,T16,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T20
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T20
0	1	Covered	T3,T8,T20
1	0	Covered	T3,T8,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T8,T11,T14
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T14
0	1	Covered	T8,T11,T14
1	0	Covered	T8,T11,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T14,T16
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T16
0	1	Covered	T3,T14,T16
1	0	Covered	T3,T14,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T14,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T14,T16
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T16
0	1	Covered	T3,T14,T16
1	0	Covered	T3,T14,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T8,T16,T20
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T16,T20
0	1	Covered	T8,T16,T20
1	0	Covered	T8,T16,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T8,T16,T123
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T16,T123
0	1	Covered	T8,T16,T123
1	0	Covered	T8,T16,T123

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T11,T16,T20
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T16,T20
0	1	Covered	T11,T16,T20
1	0	Covered	T11,T16,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T20
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T20
0	1	Covered	T3,T8,T20
1	0	Covered	T3,T8,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T8,T11,T14
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T14
0	1	Covered	T8,T11,T14
1	0	Covered	T8,T11,T14

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T14,T16
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T16
0	1	Covered	T3,T14,T16
1	0	Covered	T3,T14,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T16,T20
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T2,T3,T8
1	1	1	Covered	T2,T3,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T2,T3,T9
1	1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T9

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T2,T9,T12
1	1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T12
0	1	Covered	T2,T9,T12
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T12

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T2,T8,T9
1	1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T2,T3,T8
1	1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T9,T11
1	1	0	Covered	T2,T9,T11
1	1	1	Covered	T2,T9,T11

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T11

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T11

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T2,T8,T9
1	1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T2,T3,T8
1	1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T8,T9

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T8,T9

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T9,T11

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T8,T9

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T5
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T16,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T16,T123

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T16,T123

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T16,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T16,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T11,T14

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T11,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32739193	32414360	0	0
gen_filter_match[0].MatchCheck00_A	32739193	9481791	0	0
gen_filter_match[0].MatchCheck01_A	32739193	2163084	0	0
gen_filter_match[0].MatchCheck10_A	32739193	2623104	0	0
gen_filter_match[0].MatchCheck11_A	32739193	18146381	0	0
gen_filter_match[1].MatchCheck00_A	32739193	11053365	0	0
gen_filter_match[1].MatchCheck01_A	32739193	1179139	0	0
gen_filter_match[1].MatchCheck10_A	32739193	1536913	0	0
gen_filter_match[1].MatchCheck11_A	32739193	18644943	0	0
gen_filter_match[2].MatchCheck00_A	32739193	11319870	0	0
gen_filter_match[2].MatchCheck01_A	32739193	431655	0	0
gen_filter_match[2].MatchCheck10_A	32739193	489441	0	0
gen_filter_match[2].MatchCheck11_A	32739193	20173394	0	0
gen_filter_match[3].MatchCheck00_A	32739193	11832034	0	0
gen_filter_match[3].MatchCheck01_A	32739193	302505	0	0
gen_filter_match[3].MatchCheck10_A	32739193	493232	0	0
gen_filter_match[3].MatchCheck11_A	32739193	19786589	0	0
gen_filter_match[4].MatchCheck00_A	32739193	12426365	0	0
gen_filter_match[4].MatchCheck01_A	32739193	32505	0	0
gen_filter_match[4].MatchCheck10_A	32739193	64145	0	0
gen_filter_match[4].MatchCheck11_A	32739193	19891345	0	0
gen_filter_match[5].MatchCheck00_A	32739193	12958226	0	0
gen_filter_match[5].MatchCheck01_A	32739193	32058	0	0
gen_filter_match[5].MatchCheck10_A	32739193	94	0	0
gen_filter_match[5].MatchCheck11_A	32739193	19423982	0	0
gen_filter_match[6].MatchCheck00_A	32739193	11405470	0	0
gen_filter_match[6].MatchCheck01_A	32739193	32244	0	0
gen_filter_match[6].MatchCheck10_A	32739193	65023	0	0
gen_filter_match[6].MatchCheck11_A	32739193	20911623	0	0
gen_filter_match[7].MatchCheck00_A	32739193	12516127	0	0
gen_filter_match[7].MatchCheck01_A	32739193	128936	0	0
gen_filter_match[7].MatchCheck10_A	32739193	103728	0	0
gen_filter_match[7].MatchCheck11_A	32739193	19665569	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	32414360	0	0
T1	1196	1114	0	0
T2	32636	32564	0	0
T3	34664	34488	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	63899	0	0
T9	33964	33866	0	0
T10	15407	13574	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	9481791	0	0
T1	1196	1114	0	0
T2	32636	4	0	0
T3	34664	1113	0	0
T4	7693	7616	0	0
T5	24781	21636	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	32240	0	0
T9	33964	3	0	0
T10	15407	12687	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	2163084	0	0
T19	0	33509	0	0
T20	100401	32933	0	0
T21	66158	32772	0	0
T22	65603	32690	0	0
T24	15475	0	0	0
T35	0	32424	0	0
T122	1037	0	0	0
T123	98436	0	0	0
T124	0	31546	0	0
T125	0	32734	0	0
T126	0	6174	0	0
T127	0	33421	0	0
T128	0	32158	0	0
T129	97704	0	0	0
T130	98253	0	0	0
T131	1188	0	0	0
T132	98834	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	2623104	0	0
T2	32636	1	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	0	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T14	0	33297	0	0
T16	0	33641	0	0
T18	0	13733	0	0
T35	0	1	0	0
T130	0	1	0	0
T133	0	32908	0	0
T134	0	1	0	0
T135	0	33726	0	0
T136	0	33086	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	18146381	0	0
T2	32636	32559	0	0
T3	34664	33375	0	0
T4	7693	0	0	0
T5	24781	148	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	31659	0	0
T9	33964	33863	0	0
T10	15407	887	0	0
T11	34319	0	0	0
T12	0	66046	0	0
T13	0	33062	0	0
T14	0	32776	0	0
T15	0	66145	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	11053365	0	0
T1	1196	1114	0	0
T2	32636	4	0	0
T3	34664	1113	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	32240	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	1179139	0	0
T16	98669	32451	0	0
T20	100401	0	0	0
T24	15475	0	0	0
T35	0	33490	0	0
T42	69	0	0	0
T55	0	32606	0	0
T119	0	32447	0	0
T122	1037	0	0	0
T123	98436	0	0	0
T124	0	32121	0	0
T129	97704	0	0	0
T130	98253	0	0	0
T133	0	1	0	0
T137	0	32881	0	0
T138	0	33843	0	0
T139	0	33586	0	0
T140	0	33114	0	0
T141	32245	0	0	0
T142	99894	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	1536913	0	0
T2	32636	2	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	31659	0	0
T9	33964	0	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T16	0	32500	0	0
T34	0	6	0	0
T35	0	1	0	0
T119	0	33082	0	0
T130	0	1	0	0
T134	0	32599	0	0
T143	0	31985	0	0
T144	0	33437	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	18644943	0	0
T2	32636	32558	0	0
T3	34664	33375	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	33863	0	0
T10	15407	0	0	0
T11	34319	34222	0	0
T12	0	66046	0	0
T13	0	33062	0	0
T14	0	66073	0	0
T15	0	66145	0	0
T16	0	33641	0	0
T141	0	32175	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	11319870	0	0
T1	1196	1114	0	0
T2	32636	4	0	0
T3	34664	34488	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	31663	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	431655	0	0
T35	97608	1	0	0
T118	72643	0	0	0
T119	68014	0	0	0
T124	63767	0	0	0
T134	66075	1	0	0
T135	67089	0	0	0
T143	65964	0	0	0
T145	0	33437	0	0
T146	0	32784	0	0
T147	0	32446	0	0
T148	0	1	0	0
T149	0	31603	0	0
T150	0	32652	0	0
T151	0	32112	0	0
T152	0	32874	0	0
T153	64877	0	0	0
T154	34129	0	0	0
T155	27014	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	489441	0	0
T2	32636	2	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	32236	0	0
T9	33964	0	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T35	0	1	0	0
T123	0	32861	0	0
T130	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T136	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	20173394	0	0
T2	32636	32558	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	33863	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	66046	0	0
T13	0	33062	0	0
T14	0	66073	0	0
T15	0	66145	0	0
T16	0	64951	0	0
T20	0	32933	0	0
T141	0	32175	0	0
T142	0	99840	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	11832034	0	0
T1	1196	1114	0	0
T2	32636	4	0	0
T3	34664	34488	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	32240	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	302505	0	0
T21	66158	0	0	0
T22	65603	0	0	0
T26	0	7682	0	0
T122	1037	0	0	0
T123	98436	1	0	0
T130	98253	0	0	0
T131	1188	0	0	0
T132	98834	0	0	0
T133	97790	0	0	0
T134	0	1	0	0
T146	0	31419	0	0
T147	0	33484	0	0
T148	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	33490	0	0
T161	0	1	0	0
T162	97639	0	0	0
T163	32014	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	493232	0	0
T2	32636	2	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	1	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T35	0	31640	0	0
T119	0	1	0	0
T123	0	1	0	0
T130	0	1	0	0
T134	0	1	0	0
T157	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	19786589	0	0
T2	32636	32558	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	31659	0	0
T9	33964	33862	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	66046	0	0
T13	0	33062	0	0
T14	0	32776	0	0
T15	0	66145	0	0
T16	0	66092	0	0
T141	0	32175	0	0
T142	0	99840	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	12426365	0	0
T1	1196	1114	0	0
T2	32636	4	0	0
T3	34664	1113	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	31663	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	32505	0	0
T34	11233	0	0	0
T35	97608	1	0	0
T118	72643	0	0	0
T133	97790	1	0	0
T134	66075	0	0	0
T143	65964	0	0	0
T148	0	1	0	0
T156	32711	0	0	0
T161	0	2	0	0
T162	97639	0	0	0
T163	32014	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	32495	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	809	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	64145	0	0
T2	32636	2	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	1	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	1	0	0
T35	0	1	0	0
T119	0	2	0	0
T123	0	1	0	0
T130	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T156	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	19891345	0	0
T2	32636	32558	0	0
T3	34664	33375	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	32236	0	0
T9	33964	33862	0	0
T10	15407	0	0	0
T11	34319	34222	0	0
T12	0	66045	0	0
T13	0	33062	0	0
T14	0	33297	0	0
T15	0	66145	0	0
T141	0	32175	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	12958226	0	0
T1	1196	1114	0	0
T2	32636	5	0	0
T3	34664	34488	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	63899	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	32058	0	0
T35	97608	1	0	0
T118	72643	0	0	0
T119	68014	0	0	0
T124	63767	0	0	0
T134	66075	0	0	0
T135	67089	0	0	0
T136	0	1	0	0
T143	65964	0	0	0
T153	64877	0	0	0
T154	34129	0	0	0
T155	27014	0	0	0
T161	0	1	0	0
T166	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	94	0	0
T2	32636	1	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	1	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	1	0	0
T35	0	2	0	0
T123	0	1	0	0
T130	0	1	0	0
T133	0	1	0	0
T157	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	19423982	0	0
T2	32636	32558	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	33862	0	0
T10	15407	0	0	0
T11	34319	34222	0	0
T12	0	66045	0	0
T13	0	33062	0	0
T14	0	33297	0	0
T15	0	66145	0	0
T16	0	33641	0	0
T141	0	32175	0	0
T142	0	99840	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	11405470	0	0
T1	1196	1114	0	0
T2	32636	5	0	0
T3	34664	34488	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	31663	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	32244	0	0
T21	66158	0	0	0
T22	65603	0	0	0
T35	0	1	0	0
T122	1037	0	0	0
T123	98436	1	0	0
T130	98253	0	0	0
T131	1188	0	0	0
T132	98834	0	0	0
T133	97790	0	0	0
T136	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T162	97639	0	0	0
T163	32014	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T179	0	32231	0	0
T180	0	1	0	0
T181	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	65023	0	0
T2	32636	1	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	1	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	1	0	0
T35	0	2	0	0
T119	0	2	0	0
T123	0	1	0	0
T130	0	1	0	0
T133	0	1	0	0
T156	0	2	0	0
T164	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	20911623	0	0
T2	32636	32558	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	32236	0	0
T9	33964	33862	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	66045	0	0
T13	0	33062	0	0
T14	0	66073	0	0
T15	0	66145	0	0
T16	0	66141	0	0
T141	0	32175	0	0
T142	0	99840	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	12516127	0	0
T1	1196	1114	0	0
T2	32636	5	0	0
T3	34664	1113	0	0
T4	7693	7616	0	0
T5	24781	21784	0	0
T6	1135	1064	0	0
T7	7301	7212	0	0
T8	63955	4	0	0
T9	33964	3	0	0
T10	15407	13574	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	128936	0	0
T14	66138	32776	0	0
T15	66248	0	0	0
T16	98669	0	0	0
T20	100401	0	0	0
T23	25634	0	0	0
T41	85	0	0	0
T42	69	0	0	0
T121	1117	0	0	0
T123	0	1	0	0
T136	0	1	0	0
T141	32245	0	0	0
T142	99894	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0
T166	0	1	0	0
T174	0	1	0	0
T182	0	32529	0	0
T183	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	103728	0	0
T2	32636	1	0	0
T3	34664	0	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	0	0	0
T9	33964	1	0	0
T10	15407	0	0	0
T11	34319	0	0	0
T12	0	1	0	0
T34	0	5847	0	0
T35	0	2	0	0
T119	0	2	0	0
T123	0	1	0	0
T130	0	1	0	0
T156	0	2	0	0
T164	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32739193	19665569	0	0
T2	32636	32558	0	0
T3	34664	33375	0	0
T4	7693	0	0	0
T5	24781	0	0	0
T6	1135	0	0	0
T7	7301	0	0	0
T8	63955	63895	0	0
T9	33964	33862	0	0
T10	15407	0	0	0
T11	34319	34222	0	0
T12	0	66045	0	0
T13	0	33062	0	0
T14	0	33297	0	0
T15	0	66145	0	0
T16	0	32500	0	0