Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13931	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	3133	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	3348	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	3263	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	3195	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	3142	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	3116	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	3192	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	3070	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	3112	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2841	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	3082	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	3115	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	3047	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	3175	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	3307	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	3384	0	0
adc_en_ctl_rd_A	2147483647	2595	0	0
adc_fsm_rst_rd_A	2147483647	2105	0	0
adc_intr_ctl_rd_A	2147483647	2719	0	0
adc_lp_sample_ctl_rd_A	2147483647	2166	0	0
adc_pd_ctl_rd_A	2147483647	2925	0	0
adc_sample_ctl_rd_A	2147483647	2190	0	0
adc_wakeup_ctl_rd_A	2147483647	2193	0	0
intr_enable_rd_A	2147483647	3171	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13931	0	0
T18	522476	1	0	0
T19	611263	0	0	0
T26	0	1	0	0
T40	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T136	688427	0	0	0
T146	803315	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	668177	0	0	0
T190	966850	0	0	0
T191	123820	0	0	0
T192	923746	0	0	0
T193	508295	0	0	0
T194	273204	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3133	0	0
T17	453228	21	0	0
T39	0	46	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	25	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	37	0	0
T195	0	12	0	0
T196	0	28	0	0
T197	0	19	0	0
T198	0	12	0	0
T199	0	38	0	0
T200	0	30	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3348	0	0
T17	453228	32	0	0
T39	0	21	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	33	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	27	0	0
T195	0	16	0	0
T196	0	32	0	0
T197	0	4	0	0
T198	0	21	0	0
T199	0	5	0	0
T200	0	37	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3263	0	0
T17	453228	21	0	0
T39	0	40	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	31	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	29	0	0
T195	0	15	0	0
T196	0	17	0	0
T197	0	33	0	0
T198	0	25	0	0
T199	0	3	0	0
T200	0	27	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3195	0	0
T17	453228	37	0	0
T39	0	52	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	56	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	24	0	0
T195	0	17	0	0
T196	0	21	0	0
T197	0	15	0	0
T198	0	31	0	0
T199	0	9	0	0
T200	0	17	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3142	0	0
T17	453228	28	0	0
T39	0	23	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	55	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	25	0	0
T195	0	17	0	0
T196	0	31	0	0
T197	0	12	0	0
T198	0	16	0	0
T199	0	7	0	0
T200	0	41	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3116	0	0
T17	453228	27	0	0
T39	0	31	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	31	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	44	0	0
T195	0	18	0	0
T196	0	26	0	0
T197	0	26	0	0
T198	0	18	0	0
T199	0	28	0	0
T200	0	26	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3192	0	0
T17	453228	15	0	0
T39	0	38	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	58	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	20	0	0
T195	0	24	0	0
T196	0	30	0	0
T197	0	29	0	0
T198	0	6	0	0
T199	0	35	0	0
T200	0	14	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3070	0	0
T17	453228	26	0	0
T39	0	22	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	25	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	16	0	0
T195	0	20	0	0
T196	0	20	0	0
T197	0	18	0	0
T198	0	19	0	0
T199	0	10	0	0
T200	0	24	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3112	0	0
T17	453228	28	0	0
T39	0	25	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	31	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	27	0	0
T195	0	18	0	0
T196	0	21	0	0
T197	0	11	0	0
T198	0	20	0	0
T199	0	10	0	0
T200	0	28	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2841	0	0
T17	453228	26	0	0
T39	0	20	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	37	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	18	0	0
T195	0	13	0	0
T196	0	43	0	0
T197	0	26	0	0
T198	0	16	0	0
T199	0	13	0	0
T200	0	25	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3082	0	0
T17	453228	14	0	0
T39	0	31	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	54	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	23	0	0
T195	0	16	0	0
T196	0	38	0	0
T197	0	28	0	0
T198	0	12	0	0
T199	0	25	0	0
T200	0	38	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3115	0	0
T17	453228	28	0	0
T39	0	30	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	24	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	23	0	0
T195	0	11	0	0
T196	0	38	0	0
T197	0	28	0	0
T198	0	18	0	0
T199	0	12	0	0
T200	0	20	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3047	0	0
T17	453228	39	0	0
T39	0	47	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	23	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	31	0	0
T195	0	9	0	0
T196	0	14	0	0
T197	0	14	0	0
T198	0	23	0	0
T199	0	26	0	0
T200	0	38	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3175	0	0
T17	453228	30	0	0
T39	0	21	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	41	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	18	0	0
T195	0	22	0	0
T196	0	17	0	0
T197	0	28	0	0
T198	0	26	0	0
T199	0	22	0	0
T200	0	34	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3307	0	0
T17	453228	35	0	0
T39	0	31	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	26	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	22	0	0
T195	0	19	0	0
T196	0	39	0	0
T197	0	19	0	0
T198	0	20	0	0
T199	0	11	0	0
T200	0	35	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3384	0	0
T17	453228	27	0	0
T39	0	29	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	48	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	31	0	0
T195	0	25	0	0
T196	0	51	0	0
T197	0	26	0	0
T198	0	14	0	0
T199	0	30	0	0
T200	0	36	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2595	0	0
T17	453228	17	0	0
T39	0	33	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	40	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	26	0	0
T195	0	4	0	0
T196	0	38	0	0
T197	0	21	0	0
T198	0	33	0	0
T199	0	15	0	0
T200	0	17	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T17	453228	25	0	0
T39	0	12	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	33	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	19	0	0
T195	0	19	0	0
T196	0	19	0	0
T197	0	8	0	0
T198	0	15	0	0
T199	0	37	0	0
T200	0	34	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2719	0	0
T17	453228	17	0	0
T39	0	36	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	43	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	38	0	0
T195	0	28	0	0
T196	0	31	0	0
T197	0	22	0	0
T198	0	18	0	0
T199	0	33	0	0
T200	0	28	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2166	0	0
T17	453228	38	0	0
T39	0	17	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	39	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	29	0	0
T195	0	26	0	0
T196	0	39	0	0
T197	0	13	0	0
T198	0	14	0	0
T199	0	20	0	0
T200	0	24	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2925	0	0
T17	453228	24	0	0
T39	0	34	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	30	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	35	0	0
T195	0	34	0	0
T196	0	34	0	0
T197	0	15	0	0
T198	0	20	0	0
T199	0	23	0	0
T200	0	23	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2190	0	0
T17	453228	22	0	0
T39	0	34	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	39	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	14	0	0
T195	0	18	0	0
T196	0	20	0	0
T197	0	20	0	0
T198	0	19	0	0
T199	0	32	0	0
T200	0	19	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2193	0	0
T17	453228	16	0	0
T39	0	37	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	39	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	47	0	0
T195	0	30	0	0
T196	0	42	0	0
T197	0	6	0	0
T198	0	14	0	0
T199	0	21	0	0
T200	0	25	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3171	0	0
T17	453228	83	0	0
T39	0	45	0	0
T43	4802	0	0	0
T44	52654	0	0	0
T60	0	47	0	0
T144	333632	0	0	0
T157	779995	0	0	0
T165	116293	0	0	0
T185	0	29	0	0
T195	0	17	0	0
T196	0	105	0	0
T197	0	37	0	0
T198	0	16	0	0
T199	0	54	0	0
T201	317573	0	0	0
T202	157140	0	0	0
T203	654721	0	0	0
T204	211067	0	0	0
T205	0	17	0	0