Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1122561

1

T1

51

T2

58

T3

900

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2008199	1			T1	82		T2	82		T3	1682
values[0x0]	141974	1			T1	26		T2	32		T3	84
values[0x1]	142434	1			T1	38		T2	32		T3	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	942709	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1349898

1

T1

64

T2

72

T3

1077

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6943	1			T3	4		T5	21		T6	65
valid_sources[0x01]	11045	1			T3	8		T5	14		T6	4
valid_sources[0x02]	8746	1			T3	4		T4	7		T5	8
valid_sources[0x03]	7862	1			T3	3		T4	5		T5	5
valid_sources[0x04]	7888	1			T1	2		T3	7		T4	3
valid_sources[0x05]	11854	1			T1	1		T3	7		T4	8
valid_sources[0x06]	10611	1			T1	1		T3	3		T4	6
valid_sources[0x07]	6681	1			T3	4		T4	11		T5	16
valid_sources[0x08]	10969	1			T3	3		T4	9		T5	8
valid_sources[0x09]	9820	1			T3	6		T5	8		T6	6
valid_sources[0x0a]	12022	1			T1	1		T3	3		T5	14
valid_sources[0x0b]	6873	1			T1	1		T3	9		T4	19
valid_sources[0x0c]	7119	1			T1	1		T3	10		T5	10
valid_sources[0x0d]	11697	1			T3	5		T4	6		T5	13
valid_sources[0x0e]	7923	1			T3	5		T5	9		T7	1
valid_sources[0x0f]	7777	1			T3	4		T5	8		T6	7
valid_sources[0x10]	7046	1			T1	1		T3	3		T5	10
valid_sources[0x11]	6891	1			T3	1		T4	5		T5	8
valid_sources[0x12]	9651	1			T1	1		T3	4		T4	1
valid_sources[0x13]	7150	1			T4	1		T5	16		T6	3
valid_sources[0x14]	6870	1			T1	1		T3	2		T5	10
valid_sources[0x15]	9690	1			T3	3		T5	14		T6	8
valid_sources[0x16]	6760	1			T1	1		T3	2		T5	7
valid_sources[0x17]	7187	1			T3	4		T4	3		T5	11
valid_sources[0x18]	6888	1			T5	15		T6	2		T7	1
valid_sources[0x19]	15854	1			T1	1		T3	3		T4	5
valid_sources[0x1a]	7576	1			T1	2		T4	7		T5	10
valid_sources[0x1b]	12985	1			T1	2		T3	6		T4	22
valid_sources[0x1c]	7960	1			T1	6		T3	3		T4	17
valid_sources[0x1d]	18362	1			T3	4		T4	14		T5	15
valid_sources[0x1e]	7593	1			T3	2		T5	3		T6	3
valid_sources[0x1f]	7140	1			T1	3		T3	9		T5	30
valid_sources[0x20]	7152	1			T3	7		T5	4		T6	3
valid_sources[0x21]	7199	1			T1	1		T3	4		T4	23
valid_sources[0x22]	8992	1			T1	3		T5	13		T6	2
valid_sources[0x23]	6898	1			T1	3		T3	4		T5	5
valid_sources[0x24]	11140	1			T4	5		T5	8		T6	63
valid_sources[0x25]	18424	1			T3	8		T4	13		T5	14
valid_sources[0x26]	15160	1			T3	4		T4	12		T5	5
valid_sources[0x27]	6965	1			T1	2		T3	5		T4	14
valid_sources[0x28]	7025	1			T3	1		T5	10		T6	5
valid_sources[0x29]	11331	1			T3	6		T5	11		T6	3
valid_sources[0x2a]	7020	1			T3	2		T4	1		T5	11
valid_sources[0x2b]	12017	1			T3	7		T5	7		T6	15
valid_sources[0x2c]	9058	1			T3	5		T5	5		T6	2
valid_sources[0x2d]	6803	1			T3	2		T4	6		T5	19
valid_sources[0x2e]	14265	1			T1	2		T3	3		T5	8
valid_sources[0x2f]	16440	1			T3	1		T4	1		T5	15
valid_sources[0x30]	15105	1			T1	2		T3	4		T5	4
valid_sources[0x31]	6405	1			T3	4		T5	6		T6	12
valid_sources[0x32]	11496	1			T3	2		T5	1		T6	5
valid_sources[0x33]	6662	1			T3	2		T4	12		T5	15
valid_sources[0x34]	7225	1			T1	1		T3	5		T5	21
valid_sources[0x35]	7751	1			T3	2		T4	4		T5	6
valid_sources[0x36]	8242	1			T3	3		T5	10		T6	6
valid_sources[0x37]	6697	1			T3	2		T4	6		T5	4
valid_sources[0x38]	22454	1			T3	4		T5	5		T9	26
valid_sources[0x39]	7439	1			T3	2		T4	4		T5	9
valid_sources[0x3a]	7790	1			T3	4		T4	5		T5	11
valid_sources[0x3b]	7302	1			T3	1		T4	14		T5	11
valid_sources[0x3c]	11148	1			T1	1		T3	3		T4	7
valid_sources[0x3d]	9642	1			T1	2		T5	4		T6	41
valid_sources[0x3e]	7499	1			T3	9		T4	19		T5	7
valid_sources[0x3f]	11336	1			T3	5		T4	1		T5	18
valid_sources[0x40]	11030	1			T3	7		T5	11		T6	3
valid_sources[0x41]	8789	1			T3	1		T5	13		T6	4
valid_sources[0x42]	7936	1			T1	4		T3	3		T4	8
valid_sources[0x43]	12937	1			T3	2		T4	21		T5	7
valid_sources[0x44]	7319	1			T3	6		T4	10		T5	7
valid_sources[0x45]	11314	1			T3	2		T4	7		T5	12
valid_sources[0x46]	8900	1			T3	4		T5	3		T6	5
valid_sources[0x47]	7923	1			T3	1		T4	4		T5	22
valid_sources[0x48]	7080	1			T3	2		T5	12		T6	4
valid_sources[0x49]	6555	1			T3	4		T4	13		T5	13
valid_sources[0x4a]	7587	1			T3	5		T4	3		T5	13
valid_sources[0x4b]	7773	1			T3	5		T4	25		T5	20
valid_sources[0x4c]	7727	1			T1	1		T3	4		T4	1
valid_sources[0x4d]	6970	1			T3	5		T5	12		T9	22
valid_sources[0x4e]	7264	1			T3	7		T4	3		T5	22
valid_sources[0x4f]	11000	1			T1	2		T3	2		T4	12
valid_sources[0x50]	7345	1			T1	2		T3	9		T4	6
valid_sources[0x51]	9421	1			T3	2		T4	1		T5	13
valid_sources[0x52]	17609	1			T1	1		T3	5		T4	3
valid_sources[0x53]	11507	1			T3	4		T5	19		T6	23
valid_sources[0x54]	7090	1			T3	4		T5	8		T6	6
valid_sources[0x55]	7637	1			T1	2		T3	3		T5	5
valid_sources[0x56]	12551	1			T1	1		T3	2		T4	5
valid_sources[0x57]	7183	1			T3	4		T5	14		T6	3
valid_sources[0x58]	7135	1			T1	1		T3	3		T5	18
valid_sources[0x59]	9175	1			T3	2		T4	1		T5	6
valid_sources[0x5a]	8512	1			T3	5		T5	18		T6	2
valid_sources[0x5b]	6995	1			T3	3		T5	12		T6	5
valid_sources[0x5c]	7674	1			T1	1		T3	8		T5	15
valid_sources[0x5d]	6863	1			T3	5		T5	19		T9	19
valid_sources[0x5e]	15510	1			T3	2		T5	11		T6	45
valid_sources[0x5f]	7118	1			T3	1		T4	12		T5	10
valid_sources[0x60]	7785	1			T3	3		T4	14		T5	8
valid_sources[0x61]	7058	1			T3	7		T5	11		T6	4
valid_sources[0x62]	7292	1			T1	2		T3	2		T4	1
valid_sources[0x63]	7514	1			T3	3		T5	13		T6	5
valid_sources[0x64]	6834	1			T3	5		T4	5		T5	23
valid_sources[0x65]	8681	1			T1	3		T4	12		T5	2
valid_sources[0x66]	7056	1			T5	24		T9	25		T10	11
valid_sources[0x67]	6754	1			T3	3		T5	8		T6	4
valid_sources[0x68]	6954	1			T3	2		T4	5		T5	15
valid_sources[0x69]	6678	1			T1	1		T4	2		T5	21
valid_sources[0x6a]	6569	1			T3	4		T4	6		T5	7
valid_sources[0x6b]	14054	1			T3	3		T4	3		T5	4
valid_sources[0x6c]	10501	1			T1	2		T3	4		T4	4
valid_sources[0x6d]	7801	1			T3	5		T4	31		T5	8
valid_sources[0x6e]	6783	1			T3	2		T4	11		T5	9
valid_sources[0x6f]	7769	1			T3	1		T4	7		T5	7
valid_sources[0x70]	6939	1			T1	1		T3	1		T4	4
valid_sources[0x71]	10685	1			T1	2		T3	6		T4	11
valid_sources[0x72]	10768	1			T3	2		T5	16		T7	1
valid_sources[0x73]	7167	1			T3	4		T4	4		T5	14
valid_sources[0x74]	7079	1			T1	1		T3	4		T4	6
valid_sources[0x75]	7089	1			T1	2		T3	3		T5	18
valid_sources[0x76]	7305	1			T1	1		T3	4		T4	7
valid_sources[0x77]	6964	1			T3	5		T4	13		T5	9
valid_sources[0x78]	12641	1			T3	1		T4	3		T5	10
valid_sources[0x79]	6968	1			T1	2		T3	4		T5	8
valid_sources[0x7a]	6925	1			T3	2		T4	4		T5	4
valid_sources[0x7b]	7435	1			T1	2		T3	11		T4	9
valid_sources[0x7c]	11207	1			T1	1		T3	6		T4	1
valid_sources[0x7d]	6787	1			T3	3		T5	10		T6	18
valid_sources[0x7e]	6807	1			T3	4		T5	12		T6	82
valid_sources[0x7f]	8886	1			T3	5		T5	9		T6	7
valid_sources[0x80]	6683	1			T1	1		T3	4		T5	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1000281

1

T1

32

T2

37

T3

830

values[0x0]

all_enables

biggest_size

71121

1

T1

11

T2

16

T3

32

values[0x1]

all_enables

biggest_size

51159

1

T1

8

T2

5

T3

38