Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29087	1			T3	11		T4	4		T5	23
auto[PWRUP]	127	1			T14	1		T19	1		T20	4
auto[ONEST_0]	73	1			T6	1		T19	1		T20	1
auto[ONEST_021]	25	1			T19	1		T22	2		T123	1
auto[ONEST_1]	87	1			T22	1		T21	4		T368	2
auto[ONEST_DONE]	3	1			T19	1		T123	1		T369	1
auto[LP_0]	130	1			T19	3		T20	1		T21	2
auto[LP_021]	37	1			T6	1		T21	1		T368	1
auto[LP_1]	135	1			T6	1		T19	3		T20	4
auto[LP_EVAL]	72	1			T6	1		T19	5		T20	1
auto[LP_SLP]	487	1			T6	4		T19	6		T20	6
auto[LP_PWRUP]	19	1			T22	1		T21	1		T23	1
auto[NP_0]	167	1			T6	1		T19	1		T20	2
auto[NP_021]	37	1			T22	1		T21	1		T123	1
auto[NP_1]	176	1			T6	1		T19	4		T20	1
auto[NP_EVAL]	20	1			T21	1		T370	1		T227	1
auto[NP_DONE]	1	1			T371	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T368

1

T123

1

T233

1

min

28561

1

T3

11

T4

4

T5

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28571	1			T3	11		T4	4		T5	23
pow[0x1]	4	1			T52	1		T24	1		T372	1
pow[0x2]	16	1			T20	1		T22	1		T123	1
pow[0x3]	24	1			T6	2		T20	1		T22	2
pow[0x4]	71	1			T19	1		T20	2		T21	1
pow[0x5]	141	1			T14	1		T19	1		T20	2
pow[0x6]	278	1			T19	4		T20	2		T22	6
pow[0x7]	540	1			T6	4		T14	1		T19	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T6

1

T19

1

T20

1

min

28125

1

T3

11

T4

4

T5

23

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28125	1			T3	11		T4	4		T5	23
pow[0x1]	1	1			T373	1		-	-		-	-
pow[0x4]	1	1			T374	1		-	-		-	-
pow[0x6]	1	1			T372	1		-	-		-	-
pow[0x7]	2	1			T19	1		T375	1		-	-
pow[0x8]	5	1			T376	1		T177	1		T377	1
pow[0x9]	6	1			T21	1		T301	1		T232	1
pow[0xa]	16	1			T123	1		T122	1		T170	1
pow[0xb]	31	1			T20	1		T21	1		T52	1
pow[0xc]	81	1			T19	6		T20	2		T22	1
pow[0xd]	133	1			T6	1		T19	1		T20	1
pow[0xe]	286	1			T6	2		T14	1		T19	1
pow[0xf]	583	1			T6	4		T14	1		T19	12