Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2306	1			T6	23		T9	5		T14	10
auto[PWRUP]	151	1			T6	1		T19	2		T20	1
auto[ONEST_0]	58	1			T22	1		T21	2		T368	2
auto[ONEST_021]	28	1			T6	1		T22	1		T21	1
auto[ONEST_1]	89	1			T6	2		T14	2		T19	2
auto[ONEST_DONE]	4	1			T378	1		T379	1		T362	1
auto[LP_0]	125	1			T6	1		T20	2		T22	1
auto[LP_021]	27	1			T20	2		T200	1		T154	1
auto[LP_1]	138	1			T6	1		T14	1		T19	1
auto[LP_EVAL]	60	1			T6	1		T19	1		T20	2
auto[LP_SLP]	542	1			T6	6		T14	2		T19	6
auto[LP_PWRUP]	25	1			T23	1		T123	1		T380	1
auto[NP_0]	215	1			T6	4		T19	1		T20	1
auto[NP_021]	46	1			T6	1		T20	1		T22	2
auto[NP_1]	228	1			T6	3		T19	2		T20	3
auto[NP_EVAL]	32	1			T368	1		T123	2		T24	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T22

1

T154

1

T228

1

min

1903

1

T6

22

T9

5

T14

13

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1910	1			T6	23		T9	5		T14	13
pow[0x1]	14	1			T22	1		T370	1		T190	1
pow[0x2]	23	1			T20	1		T22	1		T21	1
pow[0x3]	34	1			T6	2		T20	1		T23	1
pow[0x4]	72	1			T20	2		T22	1		T21	2
pow[0x5]	132	1			T19	1		T20	1		T22	3
pow[0x6]	298	1			T6	2		T14	2		T20	7
pow[0x7]	559	1			T6	10		T19	5		T20	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

212

1

T6

1

T19

3

T20

3

min

1335

1

T6

19

T9

5

T14

12

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1339	1			T6	19		T9	5		T14	12
pow[0x1]	16	1			T35	1		T233	2		T230	1
pow[0x2]	12	1			T143	2		T60	1		T233	1
pow[0x3]	34	1			T6	2		T122	3		T170	1
pow[0x4]	45	1			T170	1		T98	1		T228	2
pow[0x5]	1	1			T381	1		-	-		-	-
pow[0x7]	3	1			T20	1		T141	1		T382	1
pow[0x8]	2	1			T382	1		T383	1		-	-
pow[0x9]	7	1			T19	1		T141	1		T168	1
pow[0xa]	17	1			T6	1		T19	1		T123	1
pow[0xb]	29	1			T20	1		T22	1		T35	1
pow[0xc]	85	1			T6	3		T19	1		T21	1
pow[0xd]	153	1			T14	1		T19	2		T20	2
pow[0xe]	323	1			T6	3		T19	3		T20	5
pow[0xf]	591	1			T6	12		T14	1		T19	7