Unified Coverage Report :: Module :: adc_ctrl_reg_top

Module : adc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.76	98.90	95.13	100.00		98.47	96.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_chn0_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_ext_0	55.19	55.56	50.00			60.00
u_adc_chn_val_0_adc_chn_value_intr_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_ext_0	55.19	55.56	50.00			60.00
u_adc_chn_val_0_cdc	75.53	95.31	57.35			89.47	60.00
u_adc_chn_val_1_adc_chn_value_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_ext_1	55.19	55.56	50.00			60.00
u_adc_chn_val_1_adc_chn_value_intr_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_ext_1	55.19	55.56	50.00			60.00
u_adc_chn_val_1_cdc	75.53	95.31	57.35			89.47	60.00
u_adc_en_ctl_adc_enable	100.00	100.00	100.00			100.00
u_adc_en_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_en_ctl_oneshot_mode	100.00	100.00	100.00			100.00
u_adc_fsm_rst	100.00	100.00	100.00			100.00
u_adc_fsm_rst_cdc	99.22	100.00	96.88			100.00	100.00
u_adc_intr_ctl	100.00	100.00	100.00			100.00
u_adc_intr_status_filter_match	100.00	100.00	100.00			100.00
u_adc_intr_status_oneshot	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_lp_mode	100.00	100.00	100.00			100.00
u_adc_pd_ctl_pwrup_time	100.00	100.00	100.00			100.00
u_adc_pd_ctl_wakeup_time	100.00	100.00	100.00			100.00
u_adc_sample_ctl	100.00	100.00	100.00			100.00
u_adc_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl	100.00	100.00	100.00			100.00
u_adc_wakeup_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_filter_status	100.00	100.00	100.00			100.00
u_filter_status_cdc	96.76	100.00	88.73			98.31	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		324	324	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	228	3	3	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	269	4	4	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	309	2	2	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	347	2	2	100.00
CONT_ASSIGN	375	1	1	100.00
ALWAYS	385	2	2	100.00
CONT_ASSIGN	413	1	1	100.00
ALWAYS	426	5	5	100.00
CONT_ASSIGN	457	1	1	100.00
ALWAYS	470	5	5	100.00
CONT_ASSIGN	501	1	1	100.00
ALWAYS	514	5	5	100.00
CONT_ASSIGN	545	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	602	5	5	100.00
CONT_ASSIGN	633	1	1	100.00
ALWAYS	646	5	5	100.00
CONT_ASSIGN	677	1	1	100.00
ALWAYS	690	5	5	100.00
CONT_ASSIGN	721	1	1	100.00
ALWAYS	734	5	5	100.00
CONT_ASSIGN	765	1	1	100.00
ALWAYS	778	5	5	100.00
CONT_ASSIGN	809	1	1	100.00
ALWAYS	822	5	5	100.00
CONT_ASSIGN	853	1	1	100.00
ALWAYS	866	5	5	100.00
CONT_ASSIGN	897	1	1	100.00
ALWAYS	910	5	5	100.00
CONT_ASSIGN	941	1	1	100.00
ALWAYS	954	5	5	100.00
CONT_ASSIGN	985	1	1	100.00
ALWAYS	998	5	5	100.00
CONT_ASSIGN	1029	1	1	100.00
ALWAYS	1042	5	5	100.00
CONT_ASSIGN	1073	1	1	100.00
ALWAYS	1086	5	5	100.00
CONT_ASSIGN	1117	1	1	100.00
ALWAYS	1133	10	10	100.00
ALWAYS	1183	10	10	100.00
ALWAYS	1227	2	2	100.00
CONT_ASSIGN	1255	1	1	100.00
ALWAYS	1268	4	4	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1375	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	3400	1	1	100.00
CONT_ASSIGN	3513	1	1	100.00
CONT_ASSIGN	3653	1	1	100.00
ALWAYS	3768	32	32	100.00
CONT_ASSIGN	3802	1	1	100.00
ALWAYS	3806	1	1	100.00
CONT_ASSIGN	3841	1	1	100.00
CONT_ASSIGN	3843	1	1	100.00
CONT_ASSIGN	3844	1	1	100.00
CONT_ASSIGN	3846	1	1	100.00
CONT_ASSIGN	3847	1	1	100.00
CONT_ASSIGN	3849	1	1	100.00
CONT_ASSIGN	3850	1	1	100.00
CONT_ASSIGN	3852	1	1	100.00
CONT_ASSIGN	3853	1	1	100.00
CONT_ASSIGN	3856	1	1	100.00
CONT_ASSIGN	3860	1	1	100.00
CONT_ASSIGN	3862	1	1	100.00
CONT_ASSIGN	3864	1	1	100.00
CONT_ASSIGN	3866	1	1	100.00
CONT_ASSIGN	3871	1	1	100.00
CONT_ASSIGN	3876	1	1	100.00
CONT_ASSIGN	3881	1	1	100.00
CONT_ASSIGN	3886	1	1	100.00
CONT_ASSIGN	3891	1	1	100.00
CONT_ASSIGN	3896	1	1	100.00
CONT_ASSIGN	3901	1	1	100.00
CONT_ASSIGN	3906	1	1	100.00
CONT_ASSIGN	3911	1	1	100.00
CONT_ASSIGN	3916	1	1	100.00
CONT_ASSIGN	3921	1	1	100.00
CONT_ASSIGN	3926	1	1	100.00
CONT_ASSIGN	3931	1	1	100.00
CONT_ASSIGN	3936	1	1	100.00
CONT_ASSIGN	3941	1	1	100.00
CONT_ASSIGN	3946	1	1	100.00
CONT_ASSIGN	3948	1	1	100.00
CONT_ASSIGN	3950	1	1	100.00
CONT_ASSIGN	3952	1	1	100.00
CONT_ASSIGN	3953	1	1	100.00
CONT_ASSIGN	3955	1	1	100.00
CONT_ASSIGN	3957	1	1	100.00
ALWAYS	3961	32	32	100.00
ALWAYS	3997	34	34	100.00
CONT_ASSIGN	4111	1	1	100.00
ALWAYS	4113	27	27	100.00
CONT_ASSIGN	4203	1	1	100.00
CONT_ASSIGN	4204	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
228	1	1
229	1	1
230	1	1
257	1	1
269	1	1
270	1	1
271	1	1
272	1	1
299	1	1
309	1	1
310	1	1
337	1	1
347	1	1
348	1	1
375	1	1
385	1	1
386	1	1
413	1	1
426	1	1
427	1	1
428	1	1
429	1	1
430	1	1
457	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
501	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
545	1	1
558	1	1
559	1	1
560	1	1
561	1	1
562	1	1
589	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
633	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
677	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
721	1	1
734	1	1
735	1	1
736	1	1
737	1	1
738	1	1
765	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
809	1	1
822	1	1
823	1	1
824	1	1
825	1	1
826	1	1
853	1	1
866	1	1
867	1	1
868	1	1
869	1	1
870	1	1
897	1	1
910	1	1
911	1	1
912	1	1
913	1	1
914	1	1
941	1	1
954	1	1
955	1	1
956	1	1
957	1	1
958	1	1
985	1	1
998	1	1
999	1	1
1000	1	1
1001	1	1
1002	1	1
1029	1	1
1042	1	1
1043	1	1
1044	1	1
1045	1	1
1046	1	1
1073	1	1
1086	1	1
1087	1	1
1088	1	1
1089	1	1
1090	1	1
1117	1	1
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1183	1	1
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1227	1	1
1228	1	1
1255	1	1
1268	1	1
1269	1	1
1270	1	1
1271	1	1
1298	1	1
1361	1	1
1375	1	1
1381	1	1
1395	1	1
3400	1	1
3513	1	1
3653	1	1
3768	1	1
3769	1	1
3770	1	1
3771	1	1
3772	1	1
3773	1	1
3774	1	1
3775	1	1
3776	1	1
3777	1	1
3778	1	1
3779	1	1
3780	1	1
3781	1	1
3782	1	1
3783	1	1
3784	1	1
3785	1	1
3786	1	1
3787	1	1
3788	1	1
3789	1	1
3790	1	1
3791	1	1
3792	1	1
3793	1	1
3794	1	1
3795	1	1
3796	1	1
3797	1	1
3798	1	1
3799	1	1
3802	1	1
3806	1	1
3841	1	1
3843	1	1
3844	1	1
3846	1	1
3847	1	1
3849	1	1
3850	1	1
3852	1	1
3853	1	1
3856	1	1
3860	1	1
3862	1	1
3864	1	1
3866	1	1
3871	1	1
3876	1	1
3881	1	1
3886	1	1
3891	1	1
3896	1	1
3901	1	1
3906	1	1
3911	1	1
3916	1	1
3921	1	1
3926	1	1
3931	1	1
3936	1	1
3941	1	1
3946	1	1
3948	1	1
3950	1	1
3952	1	1
3953	1	1
3955	1	1
3957	1	1
3961	1	1
3962	1	1
3963	1	1
3964	1	1
3965	1	1
3966	1	1
3967	1	1
3968	1	1
3969	1	1
3970	1	1
3971	1	1
3972	1	1
3973	1	1
3974	1	1
3975	1	1
3976	1	1
3977	1	1
3978	1	1
3979	1	1
3980	1	1
3981	1	1
3982	1	1
3983	1	1
3984	1	1
3985	1	1
3986	1	1
3987	1	1
3988	1	1
3989	1	1
3990	1	1
3991	1	1
3992	1	1
3997	1	1
3998	1	1
4000	1	1
4004	1	1
4008	1	1
4012	1	1
4016	1	1
4019	1	1
4022	1	1
4025	1	1
4028	1	1
4031	1	1
4034	1	1
4037	1	1
4040	1	1
4043	1	1
4046	1	1
4049	1	1
4052	1	1
4055	1	1
4058	1	1
4061	1	1
4064	1	1
4067	1	1
4070	1	1
4073	1	1
4076	1	1
4079	1	1
4082	1	1
4085	1	1
4088	1	1
4091	1	1
4095	1	1
4096	1	1
4111	1	1
4113	1	1
4114	1	1
4116	1	1
4119	1	1
4122	1	1
4125	1	1
4128	1	1
4131	1	1
4134	1	1
4137	1	1
4140	1	1
4143	1	1
4146	1	1
4149	1	1
4152	1	1
4155	1	1
4158	1	1
4161	1	1
4164	1	1
4167	1	1
4170	1	1
4173	1	1
4176	1	1
4179	1	1
4182	1	1
4185	1	1
4188	1	1
4203	1	1
4204	1	1

---

Cond Coverage for Module : adc_ctrl_reg_top

	Total	Covered	Percent
Conditions	327	327	100.00
Logical	327	327	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T38,T42
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T46,T47
1	0	Covered	T37,T38,T41

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T46,T47
0	1	0	Covered	T37,T38,T41
1	0	0	Covered	T45,T46,T47

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T37,T38,T41
0	1	0	Covered	T61,T39,T36
1	0	0	Covered	T36,T42,T78

 LINE       3769
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3770
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       3771
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       3772
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       3773
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_EN_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3774
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_PD_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3775
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3776
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_SAMPLE_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3777
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_RST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3778
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3779
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3780
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3781
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3782
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3783
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3784
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3785
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3786
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3787
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3788
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3789
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3790
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3791
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3792
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3793
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3794
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_0_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3795
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_1_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3796
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_WAKEUP_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3797
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_FILTER_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3798
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_CTL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3799
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_STATUS_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3802
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3802
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3806
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T61,T39,T36

 LINE       3806
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
31 (addr_hit[30] & ((|(4'...	Covered	T1,T2,T4
30 (addr_hit[29] & ((|(4'...	Covered	T4,T5,T6
29 (addr_hit[28] & ((|(4'...	Covered	T3,T4,T5
28 (addr_hit[27] & ((|(4'...	Covered	T4,T5,T6
27 (addr_hit[26] & ((|(4'...	Covered	T1,T2,T4
26 (addr_hit[25] & ((|(4'...	Covered	T1,T2,T4
25 (addr_hit[24] & ((|(4'...	Covered	T4,T5,T6
24 (addr_hit[23] & ((|(4'...	Covered	T4,T5,T6
23 (addr_hit[22] & ((|(4'...	Covered	T4,T5,T6
22 (addr_hit[21] & ((|(4'...	Covered	T4,T5,T6
21 (addr_hit[20] & ((|(4'...	Covered	T4,T5,T6
20 (addr_hit[19] & ((|(4'...	Covered	T4,T5,T6
19 (addr_hit[18] & ((|(4'...	Covered	T4,T5,T6
18 (addr_hit[17] & ((|(4'...	Covered	T4,T5,T6
17 (addr_hit[16] & ((|(4'...	Covered	T4,T5,T6
16 (addr_hit[15] & ((|(4'...	Covered	T4,T5,T6
15 (addr_hit[14] & ((|(4'...	Covered	T4,T5,T6
14 (addr_hit[13] & ((|(4'...	Covered	T4,T5,T6
13 (addr_hit[12] & ((|(4'...	Covered	T4,T5,T6
12 (addr_hit[11] & ((|(4'...	Covered	T4,T5,T6
11 (addr_hit[10] & ((|(4'...	Covered	T4,T5,T6
10 (addr_hit[9] & ((|(4'b...	Covered	T4,T5,T6
9 (addr_hit[8] & ((|(4'b...	Covered	T4,T5,T6
8 (addr_hit[7] & ((|(4'b...	Covered	T4,T5,T6
7 (addr_hit[6] & ((|(4'b...	Covered	T4,T5,T6
6 (addr_hit[5] & ((|(4'b...	Covered	T4,T5,T6
5 (addr_hit[4] & ((|(4'b...	Covered	T4,T5,T6
4 (addr_hit[3] & ((|(4'b...	Covered	T4,T5,T6
3 (addr_hit[2] & ((|(4'b...	Covered	T4,T5,T6
2 (addr_hit[1] & ((|(4'b...	Covered	T4,T5,T6
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       3806
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       3806
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       3806
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       3806
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       3806
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T5,T6

 LINE       3806
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       3841
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T36,T78,T80
1	1	1	Covered	T1,T2,T6

 LINE       3844
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T37,T41,T42
1	1	1	Covered	T6,T9,T11

 LINE       3847
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T36,T41,T78
1	1	1	Covered	T9,T14,T123

 LINE       3850
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T40,T42,T80
1	1	1	Covered	T15,T43,T44

 LINE       3853
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T75,T124
1	1	1	Covered	T1,T2,T3

 LINE       3856
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T36,T42,T78
1	1	1	Covered	T1,T2,T3

 LINE       3860
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T41,T42,T78
1	1	1	Covered	T3,T4,T5

 LINE       3862
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T75,T124,T125
1	1	1	Covered	T3,T4,T5

 LINE       3864
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T42,T78
1	1	1	Covered	T3,T4,T5

 LINE       3866
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T78,T80,T125
1	1	1	Covered	T3,T4,T5

 LINE       3871
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T37,T42
1	1	1	Covered	T3,T4,T5

 LINE       3876
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T61,T36,T124
1	1	1	Covered	T3,T4,T5

 LINE       3881
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T41,T42
1	1	1	Covered	T3,T4,T5

 LINE       3886
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T42,T80
1	1	1	Covered	T3,T4,T5

 LINE       3891
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T37,T75,T78
1	1	1	Covered	T3,T4,T5

 LINE       3896
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T80,T126,T125
1	1	1	Covered	T3,T4,T5

 LINE       3901
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T78,T127,T126
1	1	1	Covered	T3,T4,T5

 LINE       3906
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T38,T42
1	1	1	Covered	T3,T4,T5

 LINE       3911
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T42,T78,T124
1	1	1	Covered	T3,T4,T5

 LINE       3916
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T38,T78
1	1	1	Covered	T3,T4,T5

 LINE       3921
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T42,T128,T125
1	1	1	Covered	T3,T4,T5

 LINE       3926
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T36,T37,T42
1	1	1	Covered	T3,T4,T5

 LINE       3931
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T41,T42,T80
1	1	1	Covered	T3,T4,T5

 LINE       3936
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T42,T78,T80
1	1	1	Covered	T3,T4,T5

 LINE       3941
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T41,T78,T80
1	1	1	Covered	T3,T4,T5

 LINE       3946
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T40,T125,T129
1	1	1	Covered	T3,T4,T5

 LINE       3948
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T78,T79,T130
1	1	1	Covered	T3,T4,T5

 LINE       3950
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T36,T42,T78
1	1	1	Covered	T1,T2,T6

 LINE       3953
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T39,T42,T75
1	1	1	Covered	T1,T2,T3

 LINE       4111
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		63	63	100.00
TERNARY	3802	2	2	100.00
IF	70	3	3	100.00
CASE	3998	32	32	100.00
CASE	4114	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3802	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T45,T46,T47
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3998	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	4114	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : adc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2284952	0	0
reAfterRv	2147483647	2284952	0	0
rePulse	2147483647	2006225	0	0
wePulse	2147483647	278727	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2284952	0	0
T1	111389	146	0	0
T2	156548	146	0	0
T3	798500	1882	0	0
T4	825593	954	0	0
T5	229488	2881	0	0
T6	423949	2689	0	0
T7	293954	146	0	0
T8	349297	40	0	0
T9	713509	13998	0	0
T10	160799	2871	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2284952	0	0
T1	111389	146	0	0
T2	156548	146	0	0
T3	798500	1882	0	0
T4	825593	954	0	0
T5	229488	2881	0	0
T6	423949	2689	0	0
T7	293954	146	0	0
T8	349297	40	0	0
T9	713509	13998	0	0
T10	160799	2871	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006225	0	0
T1	111389	82	0	0
T2	156548	82	0	0
T3	798500	1682	0	0
T4	825593	844	0	0
T5	229488	2543	0	0
T6	423949	1741	0	0
T7	293954	82	0	0
T8	349297	0	0	0
T9	713509	12959	0	0
T10	160799	2573	0	0
T11	0	4037	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278727	0	0
T1	111389	64	0	0
T2	156548	64	0	0
T3	798500	200	0	0
T4	825593	110	0	0
T5	229488	338	0	0
T6	423949	948	0	0
T7	293954	64	0	0
T8	349297	40	0	0
T9	713509	1039	0	0
T10	160799	298	0	0