Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5210	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1467	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1550	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1528	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1460	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1557	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1499	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1557	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1408	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1349	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1523	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1458	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1565	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1372	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1421	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1485	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1391	0	0
adc_en_ctl_rd_A	2147483647	1272	0	0
adc_fsm_rst_rd_A	2147483647	1135	0	0
adc_intr_ctl_rd_A	2147483647	1453	0	0
adc_lp_sample_ctl_rd_A	2147483647	1257	0	0
adc_pd_ctl_rd_A	2147483647	1321	0	0
adc_sample_ctl_rd_A	2147483647	1190	0	0
adc_wakeup_ctl_rd_A	2147483647	1058	0	0
intr_enable_rd_A	2147483647	2069	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5210	0	0
T6	423949	1	0	0
T7	293954	0	0	0
T8	349297	0	0	0
T9	713509	0	0	0
T10	160799	0	0	0
T11	771372	0	0	0
T12	357744	0	0	0
T13	156956	0	0	0
T14	709007	0	0	0
T15	10568	0	0	0
T34	0	1	0	0
T60	0	3	0	0
T90	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T35	854979	20	0	0
T122	400945	19	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	49	0	0
T162	0	8	0	0
T170	670277	16	0	0
T227	0	11	0	0
T229	0	29	0	0
T230	0	12	0	0
T232	0	32	0	0
T233	0	52	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1550	0	0
T35	854979	21	0	0
T122	400945	32	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	37	0	0
T162	0	19	0	0
T170	670277	19	0	0
T227	0	17	0	0
T229	0	30	0	0
T230	0	20	0	0
T232	0	47	0	0
T233	0	22	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1528	0	0
T35	854979	12	0	0
T122	400945	0	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	56	0	0
T162	0	26	0	0
T170	670277	25	0	0
T227	0	14	0	0
T229	0	20	0	0
T230	0	29	0	0
T232	0	40	0	0
T233	0	35	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0
T239	0	16	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T35	854979	14	0	0
T122	400945	16	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	29	0	0
T162	0	26	0	0
T170	670277	11	0	0
T227	0	22	0	0
T229	0	21	0	0
T230	0	26	0	0
T232	0	26	0	0
T233	0	24	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1557	0	0
T35	854979	13	0	0
T122	400945	16	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	36	0	0
T162	0	17	0	0
T170	670277	10	0	0
T227	0	11	0	0
T229	0	16	0	0
T230	0	20	0	0
T232	0	43	0	0
T233	0	39	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1499	0	0
T35	854979	18	0	0
T122	400945	26	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	50	0	0
T162	0	14	0	0
T170	670277	15	0	0
T227	0	16	0	0
T229	0	15	0	0
T230	0	27	0	0
T232	0	42	0	0
T233	0	33	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1557	0	0
T35	854979	20	0	0
T122	400945	16	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	41	0	0
T162	0	21	0	0
T170	670277	14	0	0
T227	0	20	0	0
T229	0	31	0	0
T230	0	14	0	0
T232	0	40	0	0
T233	0	39	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408	0	0
T35	854979	12	0	0
T122	400945	9	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	65	0	0
T162	0	28	0	0
T170	670277	25	0	0
T227	0	23	0	0
T229	0	22	0	0
T230	0	23	0	0
T232	0	35	0	0
T233	0	39	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T35	854979	23	0	0
T122	400945	16	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	41	0	0
T162	0	29	0	0
T170	670277	5	0	0
T227	0	4	0	0
T229	0	34	0	0
T230	0	21	0	0
T232	0	31	0	0
T233	0	30	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T35	854979	12	0	0
T122	400945	4	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	54	0	0
T162	0	13	0	0
T170	670277	14	0	0
T227	0	14	0	0
T229	0	32	0	0
T230	0	28	0	0
T232	0	48	0	0
T233	0	22	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T35	854979	23	0	0
T122	400945	25	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	39	0	0
T162	0	17	0	0
T170	670277	11	0	0
T227	0	8	0	0
T229	0	12	0	0
T230	0	26	0	0
T232	0	27	0	0
T233	0	24	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T35	854979	19	0	0
T122	400945	18	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	35	0	0
T162	0	12	0	0
T170	670277	15	0	0
T227	0	19	0	0
T229	0	53	0	0
T230	0	24	0	0
T232	0	58	0	0
T233	0	48	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T35	854979	16	0	0
T122	400945	13	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	35	0	0
T162	0	12	0	0
T170	670277	24	0	0
T227	0	12	0	0
T229	0	27	0	0
T230	0	17	0	0
T232	0	35	0	0
T233	0	39	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T35	854979	28	0	0
T122	400945	17	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	36	0	0
T162	0	26	0	0
T170	670277	8	0	0
T227	0	10	0	0
T229	0	17	0	0
T230	0	26	0	0
T232	0	54	0	0
T233	0	25	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1485	0	0
T35	854979	25	0	0
T122	400945	10	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	34	0	0
T162	0	17	0	0
T170	670277	13	0	0
T227	0	25	0	0
T229	0	22	0	0
T230	0	19	0	0
T232	0	42	0	0
T233	0	32	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1391	0	0
T35	854979	6	0	0
T122	400945	23	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	48	0	0
T162	0	16	0	0
T170	670277	14	0	0
T227	0	16	0	0
T229	0	17	0	0
T230	0	15	0	0
T232	0	54	0	0
T233	0	16	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1272	0	0
T35	854979	21	0	0
T122	400945	19	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	39	0	0
T162	0	13	0	0
T170	670277	25	0	0
T227	0	26	0	0
T229	0	13	0	0
T230	0	12	0	0
T232	0	45	0	0
T233	0	24	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1135	0	0
T35	854979	4	0	0
T122	400945	14	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	42	0	0
T162	0	17	0	0
T170	670277	16	0	0
T227	0	12	0	0
T229	0	18	0	0
T230	0	14	0	0
T232	0	29	0	0
T233	0	29	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1453	0	0
T35	854979	27	0	0
T122	400945	13	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	39	0	0
T162	0	9	0	0
T170	670277	12	0	0
T227	0	15	0	0
T229	0	37	0	0
T230	0	15	0	0
T232	0	48	0	0
T233	0	38	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1257	0	0
T35	854979	23	0	0
T122	400945	20	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	49	0	0
T162	0	31	0	0
T170	670277	6	0	0
T227	0	19	0	0
T229	0	46	0	0
T230	0	16	0	0
T232	0	37	0	0
T233	0	39	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1321	0	0
T35	854979	31	0	0
T122	400945	28	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	35	0	0
T162	0	17	0	0
T170	670277	21	0	0
T227	0	16	0	0
T229	0	16	0	0
T230	0	18	0	0
T232	0	37	0	0
T233	0	36	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1190	0	0
T35	854979	19	0	0
T122	400945	33	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	43	0	0
T162	0	28	0	0
T170	670277	30	0	0
T227	0	13	0	0
T229	0	27	0	0
T230	0	15	0	0
T232	0	49	0	0
T233	0	35	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1058	0	0
T35	854979	17	0	0
T122	400945	17	0	0
T141	543716	0	0	0
T142	123111	0	0	0
T143	0	48	0	0
T162	0	12	0	0
T170	670277	16	0	0
T227	0	13	0	0
T229	0	24	0	0
T230	0	23	0	0
T232	0	45	0	0
T233	0	25	0	0
T234	45628	0	0	0
T235	244530	0	0	0
T236	593892	0	0	0
T237	140936	0	0	0
T238	122749	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2069	0	0
T9	713509	22	0	0
T10	160799	0	0	0
T11	771372	0	0	0
T12	357744	0	0	0
T13	156956	0	0	0
T14	709007	0	0	0
T15	10568	0	0	0
T16	101317	0	0	0
T25	358384	0	0	0
T35	0	18	0	0
T51	0	8	0	0
T59	144929	0	0	0
T122	0	23	0	0
T143	0	49	0	0
T162	0	29	0	0
T170	0	20	0	0
T227	0	42	0	0
T233	0	28	0	0
T240	0	19	0	0