Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7121	1			T2	54		T8	29		T9	73
testmodes[AdcCtrlTestmodeNormal]	5523	1			T1	2		T2	53		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5811	1			T2	52		T7	1		T8	59
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3919	1			T2	18		T8	6		T9	39
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1756	1			T2	21		T8	10		T9	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1330	1			T2	15		T8	13		T9	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1743	1			T2	18		T8	11		T9	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2022	1			T1	1		T2	19		T6	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1431	1			T2	16		T8	11		T9	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1348	1			T2	17		T8	12		T9	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1408	1			T2	13		T8	12		T9	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2801	1			T2	21		T8	34		T9	13