---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdcKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.AlertsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2147483647	80	0	0
tb.dut.IntrKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlOAReadyKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlODValidKnown	0	0	2147483647	2147483647	0	0
tb.dut.WakeKnown	0	0	2147483647	2147483647	0	0
tb.dut.adc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	2147483647	6031	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A	0	0	2147483647	1782	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A	0	0	2147483647	1888	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A	0	0	2147483647	1990	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A	0	0	2147483647	1967	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A	0	0	2147483647	1827	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A	0	0	2147483647	1774	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A	0	0	2147483647	1901	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A	0	0	2147483647	1760	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A	0	0	2147483647	1773	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A	0	0	2147483647	1895	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A	0	0	2147483647	1778	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A	0	0	2147483647	1838	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A	0	0	2147483647	1813	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A	0	0	2147483647	1724	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A	0	0	2147483647	1857	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A	0	0	2147483647	1813	0	0
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A	0	0	2147483647	1547	0	0
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A	0	0	2147483647	1405	0	0
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A	0	0	2147483647	1384	0	0
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A	0	0	2147483647	1355	0	0
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A	0	0	2147483647	1733	0	0
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A	0	0	2147483647	1178	0	0
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A	0	0	2147483647	1404	0	0
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A	0	0	2147483647	1848	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2147483647	29268050	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2147483647	4721064	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
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tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2147483647	15189668	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2147483647	5423	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2147483647	19967270	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2147483647	3910856	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2147483647	5751	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2147483647	29268159	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2147483647	4721139	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2147483647	29268159	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2147483647	4721139	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2147483647	4721139	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2147483647	4721139	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2147483647	3381	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2147483647	2765	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	917	917	0	0
tb.dut.u_adc_ctrl_core.MaxFilters_A	0	0	32397403	32080489	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A	0	0	32397403	9285916	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A	0	0	32397403	2549920	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A	0	0	32397403	2589969	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A	0	0	32397403	17654684	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A	0	0	32397403	10560451	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A	0	0	32397403	1119771	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A	0	0	32397403	1299705	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A	0	0	32397403	19100562	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A	0	0	32397403	12093695	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A	0	0	32397403	652930	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A	0	0	32397403	436636	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A	0	0	32397403	18897228	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A	0	0	32397403	11968525	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A	0	0	32397403	295829	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A	0	0	32397403	389153	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A	0	0	32397403	19426982	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A	0	0	32397403	11921444	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A	0	0	32397403	33732	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A	0	0	32397403	32959	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A	0	0	32397403	20092354	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A	0	0	32397403	12997212	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A	0	0	32397403	34011	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A	0	0	32397403	112	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A	0	0	32397403	19049154	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A	0	0	32397403	12597653	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A	0	0	32397403	168965	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A	0	0	32397403	68049	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A	0	0	32397403	19245822	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A	0	0	32397403	11390337	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A	0	0	32397403	179035	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A	0	0	32397403	246552	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A	0	0	32397403	20264565	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M	0	0	29891262	29808925	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A	0	0	29891262	163336	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A	0	0	29891262	96485	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M	0	0	29891262	29808925	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A	0	0	1196	1196	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A	0	0	29891262	6578	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A	0	0	1196	1196	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A	0	0	29891262	6578	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A	0	0	1196	1196	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A	0	0	29891262	6578	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A	0	0	1196	1196	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A	0	0	29891262	6578	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A	0	0	1196	1196	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A	0	0	29891262	6578	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A	0	0	752	752	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq	0	0	2147483647	13300	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq	0	0	32397403	13300	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A	0	0	2147483647	6666	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M	0	0	32397403	6670	0	0
tb.dut.u_reg.en2addrHit	0	0	2147483647	2399196	0	0
tb.dut.u_reg.reAfterRv	0	0	2147483647	2399196	0	0
tb.dut.u_reg.rePulse	0	0	2147483647	2106767	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1925014	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2162	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2162	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2162	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2103	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2174	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1854334	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	2073	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2073	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2073	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2014	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2085	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1849420	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	2081	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2081	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2081	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2025	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2094	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1816225	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	2085	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2085	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2085	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2024	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2098	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1799931	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	2055	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2055	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2055	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	1997	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2067	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1798697	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	2063	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2063	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2063	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2003	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2075	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1815769	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	2075	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2075	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2075	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2015	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2086	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1769856	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	2059	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2059	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2059	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2002	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2070	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1913565	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2207	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2207	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2207	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2146	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2220	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1776691	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	2031	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2031	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2031	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	1971	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2043	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1797170	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	2061	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2061	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2061	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2006	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2074	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1770781	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	2039	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2039	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2039	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	1979	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2050	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1756477	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	2055	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2055	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2055	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	1996	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2067	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1805233	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2042	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2116	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1759880	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	2080	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2080	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2080	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2020	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2093	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1763919	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	2069	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2069	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	2069	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	2011	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2081	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	639951	0	917
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	32488253	640124	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	640133	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	32488253	639839	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	624225	0	917
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	32488253	632342	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	632345	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	32488253	621389	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	31779495	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	39062	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	39062	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	39078	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	38995	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	39117	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A	0	0	2147483647	15714646	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A	0	0	2147483647	19956	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	19956	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	19956	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	19901	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	19970	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	10992977	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14270	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14270	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	14270	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	14196	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14316	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	14365794	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	18305	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	18305	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	18305	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	18245	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	18319	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	11061178	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	14180	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14308	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	1257311	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	1519	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1519	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	32488253	1519	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	1458	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1532	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A	0	0	2147483647	61591127	0	0
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A	0	0	32488253	32136216	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A	0	0	2147483647	67091	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	12255	0	917
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	32488253	12305	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	79397	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	32488253	78511	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	32488253	67033	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	67106	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	917	917	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.wePulse	0	0	2147483647	292429	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	639951	0	917
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	624225	0	917
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	32488253	12255	0	917

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	966008	966008	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	2654	2654	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	6532	6532	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	3861	3861	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	6213	6213	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	3063	3063	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	5178	5178	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	4305	4305	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	7611	7611	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1189255	1189255	847

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	966008	966008	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	2654	2654	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	6532	6532	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	3861	3861	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	6213	6213	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	3063	3063	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	5178	5178	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	4305	4305	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	7611	7611	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1189255	1189255	847